Searched refs:Reg0 (Results 1 - 7 of 7) sorted by relevance
/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 467 uint16_t Reg0; member in class:llvm::MCRegUnitRootIterator 472 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 478 return Reg0; 483 return Reg0; 489 Reg0 = Reg1;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 225 unsigned Reg0 = Op0.getReg(); local 226 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); 230 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { 232 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
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/external/llvm/lib/CodeGen/ |
H A D | TargetInstrInfoImpl.cpp | 78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; local 88 if (HasDef && Reg0 == Reg1 && 91 Reg0 = Reg2; 93 } else if (HasDef && Reg0 == Reg2 && 96 Reg0 = Reg1; 107 MI->getOperand(0).setReg(Reg0);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 599 unsigned Reg0 = MI->getOperand(0).getReg(); local 605 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) 608 if (Reg0 != Reg2) { 611 if (Reg1 != Reg0) 618 } else if (Reg0 != Reg1) { 622 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0) 628 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
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H A D | ARMISelDAGToDAG.cpp | 1643 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 1655 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0 1663 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); 1666 Ops.push_back(Reg0); 1679 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; 1692 Ops.push_back(Reg0); 1696 Ops.push_back(Reg0); 1770 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 1806 // FIXME: VST1/VST2 fixed increment doesn't need Reg0 1934 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2031 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2133 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2535 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local 2551 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); local [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 1108 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1110 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 1117 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1119 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; 1153 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1155 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; 1185 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); 1187 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 158 unsigned Reg0 = MI->getOperand(0).getReg(); local 166 if (Reg0 == Reg1) { 180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); local 183 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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