Searched defs:MIB (Results 1 - 25 of 32) sorted by relevance

12

/external/llvm/lib/Target/PowerPC/
H A DPPCInstrBuilder.h33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, argument
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
H A DPPCInstrInfo.cpp686 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE)); local
687 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
688 return &*MIB;
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h320 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { argument
321 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
325 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { argument
326 return MIB.addReg(0);
330 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, argument
332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
336 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { argument
337 return MIB.addReg(0);
H A DARMInstrInfo.cpp125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, local
129 MIB.addImm(0);
130 AddDefaultPred(MIB);
H A DThumb1FrameLowering.cpp318 MachineInstrBuilder MIB = local
321 AddDefaultPred(MIB);
322 MIB.copyImplicitOps(&*MBBI);
342 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); local
343 AddDefaultPred(MIB);
361 MIB.addReg(Reg, getKillRegState(isKill));
363 MIB.setMIFlags(MachineInstr::FrameSetup);
381 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); local
382 AddDefaultPred(MIB);
392 (*MIB)
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H A DThumb1RegisterInfo.cpp130 MachineInstrBuilder MIB = local
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
263 MIB
269 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); local
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H A DThumb2ITBlockPass.cpp181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) local
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
H A DMLxExpansionPass.cpp292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) local
296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
309 MIB.addImm(Pred).addReg(PredReg);
H A DARMBaseRegisterInfo.cpp558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) local
562 AddDefaultCC(MIB);
H A DARMExpandPseudoInsts.cpp383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB
448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), local
584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); local
839 MachineInstrBuilder MIB = local
851 MachineInstrBuilder MIB = local
943 MachineInstrBuilder MIB = local
974 MachineInstrBuilder MIB = local
1006 MachineInstrBuilder MIB = local
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H A DThumb2SizeReduction.cpp467 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); local
469 MIB.addOperand(MI->getOperand(0));
470 MIB.addOperand(MI->getOperand(1));
473 MIB.addImm(OffsetImm / Scale);
478 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
483 MIB.addOperand(MI->getOperand(OpNum));
486 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
489 MIB.setMIFlags(MI->getFlags());
491 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
528 MachineInstrBuilder MIB
538 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); local
691 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
713 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
788 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); local
826 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); local
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H A DARMFrameLowering.cpp223 MachineInstrBuilder MIB = local
227 AddDefaultCC(AddDefaultPred(MIB));
447 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); local
449 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
453 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
458 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
628 MachineInstrBuilder MIB = local
632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
634 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), local
639 AddDefaultPred(MIB);
693 MachineInstrBuilder MIB = local
708 MachineInstrBuilder MIB = local
791 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) local
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/external/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(), local
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp207 MachineInstrBuilder &MIB,
226 MIB.addReg(VRBase, RegState::Define);
241 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, argument
308 const MCInstrDesc &MCID = MIB->getDesc();
340 unsigned Idx = MIB->getNumOperands();
342 MIB->getOperand(Idx-1).isReg() &&
343 MIB->getOperand(Idx-1).isImplicit())
350 MIB
206 CreateVirtualRegisters(SDNode *Node, MachineInstrBuilder &MIB, const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap<SDValue, unsigned> &VRBaseMap) argument
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/external/llvm/lib/Target/MBlaze/
H A DMBlazeFrameLowering.cpp59 MachineInstr::mop_iterator MIB = MBB->operands_begin(); local
62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
99 MachineBasicBlock::iterator MIB = MBB->begin(); local
121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
H A DMipsInstrInfo.cpp68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) local
70 return &*MIB;
109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); local
113 MIB.addReg(Cond[i].getReg());
115 MIB.addImm(Cond[i].getImm());
119 MIB.addMBB(TBB);
H A DMipsLongBranch.cpp223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); local
233 MIB.addReg(MO.getReg());
236 MIB.addMBB(MBBOpnd);
H A DMipsSEInstrInfo.cpp142 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); local
145 MIB.addReg(DestReg, RegState::Define);
148 MIB.addReg(SrcReg, getKillRegState(KillSrc));
151 MIB.addReg(ZeroReg);
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp121 MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE)) local
123 return &*MIB;
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { argument
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
98 addOffset(const MachineInstrBuilder &MIB, int Offset) { argument
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
107 addRegOffset(const MachineInstrBuilder &MIB, argument
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, argument
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
122 addFullAddress(const MachineInstrBuilder &MIB, argument
127 MIB
148 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) argument
174 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, unsigned GlobalBaseReg, unsigned char OpFlags) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE)) local
395 return &*MIB;
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp213 MachineInstrBuilder MIB; local
215 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
217 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
221 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
228 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
229 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
235 MIB->addOperand(MBBI->getOperand(i));
H A DAArch64InstrInfo.cpp123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) local
127 return &*MIB;
312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); local
314 MIB.addOperand(Cond[i]);
315 MIB.addMBB(TBB);
319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); local
321 MIB.addOperand(Cond[i]);
322 MIB.addMBB(TBB);
/external/llvm/lib/Target/R600/
H A DR600InstrInfo.cpp78 MachineInstrBuilder MIB(*MF, MI);
79 MIB.addReg(DstReg, RegState::Define);
80 MIB.addReg(AMDGPU::ALU_LITERAL_X);
81 MIB.addImm(Imm);
82 MIB.addReg(0); // PREDICATE_BIT
515 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
516 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
655 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), local
659 MIB.addImm(0) // $update_exec_mask
662 MIB
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