| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/ |
| H A D | mixcase.asm | 0 CPU SSSE3
1 CPU SSSE3 label
|
| /external/vixl/src/a64/ |
| H A D | cpu-a64.h | 34 class CPU { class in namespace:vixl
36 // Initialise CPU support.
|
| /external/chromium_org/third_party/webrtc/voice_engine/test/auto_test/ |
| H A D | voe_test_interface.h | 31 CPU = 4 enumerator in enum:voetest::TestType
|
| /external/clang/include/clang/Basic/ |
| H A D | TargetOptions.h | 30 /// If given, the name of the target CPU to generate code for.
31 std::string CPU; member in class:clang::TargetOptions
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 52 HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument
74 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, argument
76 : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
78 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
81 // Initialize scheduling itinerary for the specified CPU.
|
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430Subtarget.cpp | 28 MSP430Subtarget &MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument
33 MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &CPU, argument
35 : MSP430GenSubtargetInfo(TT, CPU, FS),
38 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
|
| H A D | MSP430TargetMachine.cpp | 28 StringRef CPU, StringRef FS,
32 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
33 Subtarget(TT, CPU, FS, *this) {
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreSubtarget.cpp | 28 XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &CPU, argument
30 : XCoreGenSubtargetInfo(TT, CPU, FS),
|
| /external/chromium_org/third_party/libvpx/source/libvpx/third_party/libyuv/source/ |
| H A D | x86inc.asm | 97 CPU amdnop label
|
| /external/chromium_org/third_party/libvpx/source/libvpx/third_party/x86inc/ |
| H A D | x86inc.asm | 188 CPU amdnop label
|
| /external/chromium_org/third_party/libyuv/source/ |
| H A D | x86inc.asm | 97 CPU amdnop label
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| H A D | AMDGPUSubtarget.cpp | 23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) {
25 InstrItins = getInstrItineraryForCPU(CPU);
30 StringRef GPU = CPU;
|
| H A D | AMDGPUTargetMachine.cpp | 42 StringRef CPU, StringRef FS,
48 LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OptLevel),
49 Subtarget(TT, CPU, FS),
41 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OptLevel ) argument
|
| /external/libvpx/libvpx/third_party/x86inc/ |
| H A D | x86inc.asm | 188 CPU amdnop label
|
| /external/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
|
| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 39 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, argument
41 // Provide the default CPU if we don't have one.
42 if (CPU.empty() && FS.size())
44 TargetName = CPU.empty() ? "sm_20" : CPU;
56 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, argument
59 : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
61 InstrInfo(initializeSubtargetDependencies(CPU, FS)),
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSubtarget.cpp | 27 SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { argument
28 std::string CPUName = CPU;
41 const std::string &CPU,
44 : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
52 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
40 SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) argument
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDGPUSubtarget.cpp | 23 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : argument
24 AMDGPUGenSubtargetInfo(TT, CPU, FS), mDumpCode(false) {
25 InstrItins = getInstrItineraryForCPU(CPU);
30 StringRef GPU = CPU;
|
| /external/chromium_org/third_party/WebKit/Source/wtf/ |
| H A D | CPU.h | 34 /* CPU() - the target CPU architecture */
35 #define CPU(WTF_FEATURE) (defined WTF_CPU_##WTF_FEATURE && WTF_CPU_##WTF_FEATURE) macro
37 /* ==== CPU() - the target CPU architecture ==== */
39 /* This defines CPU(BIG_ENDIAN) or nothing, as appropriate. */
40 /* This defines CPU(32BIT) or CPU(64BIT), as appropriate. */
42 /* CPU(X86) - i386 / x86 32-bit */
51 /* CPU(X86_6
[all...] |
| /external/chromium_org/v8/src/base/ |
| H A D | cpu.cc | 266 CPU::CPU() : stepping_(0), function in class:v8::base::CPU
297 // valid Ids in CPUInfo[0] and the CPU identification string in
298 // the other three array elements. The CPU identification string is
309 // Interpret CPU feature information.
337 // Interpret extended CPU feature information.
351 // Extract implementor from the "CPU implementer" field.
352 char* implementer = cpu_info.ExtractField("CPU implementer");
362 // Extract part number from the "CPU part" field.
363 char* part = cpu_info.ExtractField("CPU par
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64Subtarget.cpp | 45 const std::string &CPU,
48 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
50 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), CPUString(CPU),
44 AArch64Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool LittleEndian) argument
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 50 StringRef CPU,
53 InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
49 createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| H A D | AMDGPUAsmBackend.cpp | 101 StringRef CPU) {
98 createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcAsmBackend.cpp | 259 StringRef CPU) {
256 createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcSubtarget.cpp | 55 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, argument
64 std::string CPUName = CPU;
78 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument
81 : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
82 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
|