/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 33 enum CondCode { enum in namespace:llvm::Mips 73 const char *MipsFCCToString(Mips::CondCode CC);
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 32 enum CondCode { enum in namespace:llvm::X86 63 unsigned GetCondBranchFromCond(CondCode CC); 67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 75 CondCode getCondFromCMovOpc(unsigned Opc); 79 CondCode GetOppositeBranchCondition(CondCode CC);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 38 enum CondCode { enum in namespace:llvm::XCore 137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Con [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 750 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 763 enum CondCode { enum in namespace:llvm::ISD 796 inline bool isSignedIntSetCC(CondCode Code) { 802 inline bool isUnsignedIntSetCC(CondCode Code) { 809 inline bool isTrueWhenEqual(CondCode Cond) { 817 inline unsigned getUnorderedFlavor(CondCode Cond) { 823 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 827 CondCode getSetCCSwappedOperands(CondCode Operatio [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 121 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl); 493 ISD::CondCode CC, SDLoc dl) { 590 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 621 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { 653 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC, 747 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1267 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1409 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1432 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); local 1433 SDValue Ops[] = { getI32Imm(PCC), CondCode, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 168 enum CondCode enum in namespace:nv50_ir 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 60 AArch64CC::CondCode parseCondCodeString(StringRef Cond); 198 AArch64CC::CondCode Code; 242 struct CondCodeOp CondCode; member in union:__anon25952::AArch64Operand::__anon25953 274 CondCode = o.CondCode; 336 AArch64CC::CondCode getCondCode() const { 338 return CondCode.Code; 1641 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { 1643 Op->CondCode.Code = Code; 2224 AArch64CC::CondCode AArch64AsmParse [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 1771 unsigned CondCode = MI->getOperand(3).getImm(); local 1773 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode))); 1775 NewMI.addImm(CondCode);
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H A D | ARMISelLowering.cpp | 263 const ISD::CondCode Cond; 1139 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1156 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, argument 1162 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1164 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1166 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1167 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1168 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1169 case ISD::SETONE: CondCode 3181 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3373 checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps) argument 3444 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3459 ARMCC::CondCodes CondCode, CondCode2; local 3617 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); local 3653 ARMCC::CondCodes CondCode, CondCode2; local [all...] |
/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 168 enum CondCode enum in namespace:nv50_ir 587 bool compare(CondCode cc, float fval) const; 629 bool setPredicate(CondCode ccode, Value *); 679 CondCode cc; 826 void setCondition(CondCode cond) { setCond = cond; } 827 CondCode getCondition() const { return setCond; } 830 CondCode setCond;
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 786 unsigned CondCode = MI->getOperand(3).getImm(); local 799 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); 851 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { 879 static void changeFPCCToAArch64CC(ISD::CondCode CC, argument 880 AArch64CC::CondCode &CondCode, 881 AArch64CC::CondCode &CondCode2) { 888 CondCode = AArch64CC::EQ; 892 CondCode 943 changeVectorFPCCToAArch64CC(ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) argument 967 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2); local [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 192 enum CondCode { // Meaning (integer) Meaning (floating-point) enum in namespace:llvm::AArch64CC 213 inline static const char *getCondCodeName(CondCode Code) { 235 inline static CondCode getInvertedCondCode(CondCode Code) { 238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
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