Searched defs:OpIdx (Results 1 - 24 of 24) sorted by relevance

/external/llvm/include/llvm/Analysis/
H A DConstantsScanner.h28 unsigned OpIdx; // Operand index member in class:llvm::constant_iterator
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperand
[all...]
/external/llvm/utils/TableGen/
H A DCodeEmitterGen.cpp95 unsigned OpIdx; local
96 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
98 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
99 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
122 OpIdx = NumberedOp++;
125 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
136 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
143 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
203 unsigned OpIdx; local
[all...]
H A DCodeGenInstruction.cpp134 unsigned OpIdx; local
135 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
141 /// given name. If so, return true and set OpIdx to the index of the
143 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
147 OpIdx = i;
170 unsigned OpIdx = getOperandNamed(OpName); local
174 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
180 return std::make_pair(OpIdx, 0U);
184 DagInit *MIOpInfo = OperandList[OpIdx]
[all...]
H A DAsmWriterEmitter.cpp643 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { argument
644 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
647 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
1021 O << " int OpIdx = AsmString[I++] - 1;\n";
1023 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n";
1041 << " const MCInst *MI, unsigned OpIdx,\n"
1053 << " " << PrintMethods[i] << "(MI, OpIdx, OS);\n"
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h46 /// For non-data-dependent uses, OpIdx == -1.
49 int OpIdx; member in struct:llvm::PhysRegSUOper
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
/external/llvm/lib/Target/AArch64/
H A DAArch64AddressTypePromotion.cpp206 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { argument
207 if (isa<SelectInst>(Inst) && OpIdx == 0)
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx;
312 ++OpIdx) {
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
315 !shouldSExtOperand(Inst, OpIdx)) {
320 Value *Opnd = Inst->getOperand(OpIdx);
323 Inst->setOperand(OpIdx, ConstantIn
[all...]
H A DAArch64PromoteConstant.cpp234 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into
240 unsigned OpIdx) {
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1)
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0)
258 if (isa<const LoadInst>(Instr) && OpIdx > 0)
262 if (isa<const StoreInst>(Instr) && OpIdx > 1)
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0)
565 for (unsigned OpIdx
239 shouldConvertUse(const Constant *Cst, const Instruction *Instr, unsigned OpIdx) argument
[all...]
/external/llvm/lib/Target/R600/
H A DR600ExpandSpecialInstrs.cpp60 int OpIdx = TII->getOperandIdx(*OldMI, Op); local
61 if (OpIdx > -1) {
62 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
H A DAMDGPUISelDAGToDAG.cpp129 unsigned OpIdx = Desc.getNumDefs() + OpNo; local
130 if (OpIdx >= Desc.getNumOperands())
132 int RegClass = Desc.OpInfo[OpIdx].RegClass;
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp63 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
69 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
75 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
81 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
87 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
112 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
117 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
227 getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
248 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
274 getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
301 getCondBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
323 getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
343 getMemExtendOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
352 getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
371 getTestBranchTargetOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
393 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
421 getVecShifterOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
445 getSIMDShift64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
453 getSIMDShift64_32OpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
462 getSIMDShift32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
471 getSIMDShift16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
481 getFixedPointScaleOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
490 getVecShiftR64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
499 getVecShiftR32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
508 getVecShiftR16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
517 getVecShiftR8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
526 getVecShiftL64OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
535 getVecShiftL32OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
544 getVecShiftL16OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
553 getVecShiftL8OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
563 getMoveVecShifterOpValue( const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, argument
236 const MCOperand &MO = MI.getOperand(OpIdx);
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
/external/llvm/lib/CodeGen/
H A DExecutionDepsFix.cpp196 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
467 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, argument
469 int rx = regIndex(MI->getOperand(OpIdx).getReg());
555 unsigned OpIdx = UndefReads.back().second; local
563 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
564 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
571 OpIdx = UndefReads.back().second;
H A DMachineLICM.cpp248 unsigned Reg, unsigned OpIdx,
784 unsigned Reg, unsigned OpIdx,
783 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
H A DMachineInstr.cpp939 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, argument
942 assert(OpIdx < getNumOperands() && "OpIdx out of range");
945 if (OpIdx < InlineAsm::MIOp_FirstOperand)
957 if (i + NumOps > OpIdx) {
968 MachineInstr::getRegClassConstraint(unsigned OpIdx,
977 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
979 if (!getOperand(OpIdx).isReg())
984 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx,
1022 getRegClassConstraintEffectForVRegImpl( unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument
1034 getRegClassConstraintEffect( unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const argument
1723 unsigned OpIdx = DeadOps.back(); local
1788 unsigned OpIdx = DeadOps.back(); local
[all...]
H A DRegisterCoalescer.cpp655 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); local
656 NewMI->getOperand(OpIdx).setIsKill();
H A DCodeGenPrepare.cpp1674 /// \brief Utility function to determine if \p OpIdx should be promoted when
1676 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { argument
1677 if (isa<SelectInst>(Inst) && OpIdx == 0)
1876 for (int OpIdx = 0, EndOpIdx = SExtOpnd->getNumOperands(); OpIdx != EndOpIdx;
1877 ++OpIdx) {
1878 DEBUG(dbgs() << "Operand:\n" << *(SExtOpnd->getOperand(OpIdx)) << '\n');
1879 if (SExtOpnd->getOperand(OpIdx)->getType() == SExt->getType() ||
1880 !shouldSExtOperand(SExtOpnd, OpIdx)) {
1885 Value *Opnd = SExtOpnd->getOperand(OpIdx);
[all...]
/external/llvm/lib/ExecutionEngine/RuntimeDyld/
H A DRuntimeDyldChecker.cpp231 unsigned OpIdx = OpIdxExpr.getValue(); local
232 if (OpIdx >= Inst.getNumOperands()) {
235 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx)
242 const MCOperand &Op = Inst.getOperand(OpIdx);
246 ErrMsgStream << "Operand '" << format("%i", OpIdx)
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx, argument
236 const MCOperand &MO = MI.getOperand(OpIdx);
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
/external/llvm/lib/Target/ARM/
H A DARMCodeEmitter.cpp103 unsigned OpIdx);
154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
155 return getMachineOpValue(MI, MI.getOperand(OpIdx));
239 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
267 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
269 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
271 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
347 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
348 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
349 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) cons
919 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1015 unsigned OpIdx = 0; local
1117 unsigned OpIdx = 0; local
1188 unsigned OpIdx = 0; local
1273 unsigned OpIdx = 0; local
[all...]
H A DARMExpandPseudoInsts.cpp391 unsigned OpIdx = 0; local
393 bool DstIsDead = MI.getOperand(OpIdx).isDead();
394 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
406 MIB.addOperand(MI.getOperand(OpIdx++));
409 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
413 MIB.addOperand(MI.getOperand(OpIdx++));
420 SrcOpIdx = OpIdx++;
423 MIB.addOperand(MI.getOperand(OpIdx++));
424 MIB.addOperand(MI.getOperand(OpIdx
456 unsigned OpIdx = 0; local
510 unsigned OpIdx = 0; local
593 unsigned OpIdx = 0; local
1085 unsigned OpIdx = 0; local
1116 unsigned OpIdx = 0; local
[all...]
H A DARMBaseInstrInfo.cpp2589 unsigned OpIdx = Commute ? 2 : 1; local
2590 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2591 bool isKill = UseMI->getOperand(OpIdx).isKill();
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
191 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
567 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) argument
605 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
618 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
630 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
642 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
654 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
683 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
697 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
713 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
728 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
741 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
771 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
812 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
832 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
845 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &, const MCSubtargetInfo &STI) const argument
860 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
912 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
944 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
985 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
998 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1054 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1088 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1103 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1126 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1138 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1158 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1195 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1211 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1226 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1237 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1276 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
1324 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
[all...]
/external/llvm/include/llvm/IR/
H A DPatternMatch.h1116 Argument_match(unsigned OpIdx, const Opnd_t &V) : OpI(OpIdx), Val(V) { } argument
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5284 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5287 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5292 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5304 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
19831 int OpIdx = -1;
19835 OpIdx = 1;
19838 OpIdx = 0;
19839 if (OpIdx == -1)
19841 SetCC = SetCC.getOperand(OpIdx);
5286 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument

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