| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 371 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
376 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
390 if (canFoldIntoCSel(MRI, TrueReg))
414 unsigned TrueReg, unsigned FalseReg) const {
517 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
522 TrueReg = FalseReg;
536 MRI.constrainRegClass(TrueReg, RC);
540 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
369 canInsertSelect( const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
410 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
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| H A D | AArch64FastISel.cpp | 1035 unsigned TrueReg = getRegForValue(SI->getTrueValue()); local
1036 if (TrueReg == 0)
1077 .addReg(TrueReg)
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 413 /// instruction that chooses between TrueReg and FalseReg based on the
416 /// When successful, also return the latency in cycles from TrueReg,
424 /// @param TrueReg Virtual register to select when Cond is true.
427 /// @param TrueCycles Latency from TrueReg to select output.
431 unsigned TrueReg, unsigned FalseReg,
438 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when
451 /// @param TrueReg Virtual register to copy when Cond is true.
457 unsigned TrueReg, unsigned FalseReg) const {
429 canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
453 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 586 unsigned TrueReg, unsigned FalseReg,
602 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
628 unsigned TrueReg, unsigned FalseReg) const {
638 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
639 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
667 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
668 SecondReg = SwapOps ? TrueReg : FalseReg;
584 canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
624 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc dl, unsigned DestReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
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| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2973 unsigned TrueReg, unsigned FalseReg,
2987 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3011 unsigned TrueReg, unsigned FalseReg) const {
3017 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2971 canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const argument
3007 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 2620 unsigned TrueReg = MI->getOperand(1).getReg(); local
2645 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2649 .addReg(TrueReg).addMBB(StartMBB)
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