Searched defs:getReg (Results 1 - 19 of 19) sorted by relevance

/external/llvm/include/llvm/MC/
H A DMachineLocation.h54 unsigned getReg() const { return Register; } function
H A DMCInst.h62 /// getReg - Returns the register number.
63 unsigned getReg() const { function in class:llvm::MCOperand
/external/dexmaker/src/dx/java/com/android/dx/rop/code/
H A DRegisterSpec.java326 public int getReg() { method in class:RegisterSpec
442 if ((other == null) || (reg != other.getReg())) {
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h133 unsigned getReg() const { return getParent().reg; } function in class:llvm::LiveRangeEdit
156 return createEmptyIntervalFrom(getReg());
160 return createFrom(getReg());
H A DCallingConvLower.h69 static CCValAssign getReg(unsigned ValNo, MVT ValVT, function in class:llvm::CCValAssign
87 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
119 return getReg(ValNo, ValVT, 0, LocVT, HTP);
H A DMachineOperand.h263 /// getReg - Returns the register number.
264 unsigned getReg() const { function in class:llvm::MachineOperand
H A DMachineFrameInfo.h46 unsigned getReg() const { return Reg; } function in class:llvm::CalleeSavedInfo
H A DScheduleDAG.h226 /// getReg - Return the register associated with this edge. This is
229 unsigned getReg() const { function in class:llvm::SDep
231 "getReg called on non-register dependence edge!");
H A DSelectionDAGNodes.h1659 unsigned getReg() const { return Reg; } function in class:RegisterSDNode
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp91 unsigned getReg(ValueType Entry);
111 !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
134 unsigned SrcReg = I->getOperand(0).getReg();
147 MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
152 if (MO.isReg() && MO.getReg() == Reg) {
229 getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
258 Reg = MO->getReg();
287 unsigned OptimizePICCall::getReg(ValueType Entry) { function in class:OptimizePICCall
/external/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp83 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
219 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
231 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
/external/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp221 Reg = Def->getOperand(DefIdx).getReg();
226 /// When the returned value is not nullptr, getReg() gives the register
229 /// on that getReg() to access the actual value.
241 unsigned getReg() const { return Reg; } function in class:__anon25783::ValueTracker
506 if (!MO.isReg() || !MO.getReg())
538 unsigned Def = MODef.getReg();
558 Src = ValTracker.getReg();
577 if (!ShouldRewrite || Src == MI->getOperand(SrcIdx).getReg())
610 unsigned Reg = MI->getOperand(0).getReg();
631 unsigned Reg = MI->getOperand(0).getReg();
[all...]
/external/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
472 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
475 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
511 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
514 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
553 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
556 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
597 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
600 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
645 MI.addOperand(MCOperand::CreateReg(getReg(Decode
[all...]
/external/libcxxabi/src/Unwind/
H A DUnwindCursor.hpp372 virtual unw_word_t getReg(int) = 0;
400 virtual unw_word_t getReg(int);
429 (pint_t)this->getReg(UNW_REG_IP),
559 unw_word_t UnwindCursor<A, R>::getReg(int regNum) { function in class:libunwind::UnwindCursor
1140 pint_t pc = (pint_t)this->getReg(UNW_REG_IP);
1289 setReg(UNW_REG_SP, getReg(UNW_REG_SP) + _info.gp);
1303 return _addressSpace.findFunctionName((pint_t)this->getReg(UNW_REG_IP),
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp69 unsigned getReg() const { function in class:__anon25940::AArch64FastISel::Address
84 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
484 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
510 MIB.addReg(Addr.getReg());
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp255 unsigned getReg() const { function in class:__anon26012::CountValue
354 unsigned PhiOpReg = Phi->getOperand(i).getReg();
362 unsigned IndReg = DI->getOperand(1).getReg();
364 unsigned UpdReg = DI->getOperand(0).getReg();
380 unsigned PredR = Cond[CSz-1].getReg();
475 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
500 unsigned PredReg = Cond[Cond.size()-1].getReg();
528 if (Op2.isImm() || Op1.getReg() == IVReg)
565 if (!defWithImmediate(InitialValue->getReg()))
592 unsigned R = InitialValue->getReg();
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
173 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } function in class:__anon26575::RegUnitIterator
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
703 CodeGenRegister *Reg = RegBank.getReg(Order.back());
762 if (contains(RegBank.getReg(Super.Orders[i][j])))
946 getReg(Regs[i]);
959 getReg((TupRegsCopy)[j]);
1031 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { function in class:CodeGenRegBank
1318 if (Reg != UnitI.getReg()) {
[all...]
H A DDAGISelMatcher.h886 const CodeGenRegister *getReg() const { return Reg; } function in class:llvm::EmitRegisterMatcher
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp189 unsigned getReg(int RC, int RegNo);
688 unsigned getReg() const override {
1093 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1101 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1111 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1114 createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1136 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1140 createShiftOr<16, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1141 createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions);
1163 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1583 unsigned MipsAsmParser::getReg(int RC, int RegNo) { function in class:MipsAsmParser
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