/external/llvm/lib/Target/XCore/InstPrinter/ |
H A D | XCoreInstPrinter.h | 31 void printInstruction(const MCInst *MI, raw_ostream &O); 35 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 37 void printInlineJT(const MCInst *MI, int opNum, raw_ostream &O); 38 void printInlineJT32(const MCInst *MI, int opNum, raw_ostream &O); 39 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 40 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const; 87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, 100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, 104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; 109 unsigned getEncodingType(const MCInst &MI) const; 112 unsigned getEncodingBytes(const MCInst &MI) cons 131 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument 140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument 161 GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const argument 167 GPR2AlignEncode(const MCInst &MI, unsigned OpNo , SmallVectorImpl<MCFixup> &Fixup) const argument 173 GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 179 i32LiteralEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 197 SMRDmemriEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 219 VOPPostEncode(const MCInst &MI, uint64_t Value) const argument [all...] |
/external/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 44 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 46 printInstruction(MI, O); 54 void SystemZInstPrinter::printU4ImmOperand(const MCInst *MI, int OpNum, argument 56 int64_t Value = MI->getOperand(OpNum).getImm(); 61 void SystemZInstPrinter::printU6ImmOperand(const MCInst *MI, int OpNum, argument 63 int64_t Value = MI->getOperand(OpNum).getImm(); 68 void SystemZInstPrinter::printS8ImmOperand(const MCInst *MI, int OpNum, argument 70 int64_t Value = MI->getOperand(OpNum).getImm(); 75 void SystemZInstPrinter::printU8ImmOperand(const MCInst *MI, int OpNum, argument 77 int64_t Value = MI 82 printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 89 printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 96 printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 103 printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 110 printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 156 printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const; 87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, 100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, 104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; 109 unsigned getEncodingType(const MCInst &MI) const; 112 unsigned getEncodingBytes(const MCInst &MI) cons 131 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument 140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument 161 GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const argument 167 GPR2AlignEncode(const MCInst &MI, unsigned OpNo , SmallVectorImpl<MCFixup> &Fixup) const argument 173 GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 179 i32LiteralEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 197 SMRDmemriEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 219 VOPPostEncode(const MCInst &MI, uint64_t Value) const argument [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 72 bool isProfitableToTransform(const MachineInstr *MI) const; 77 void transformInstruction(MachineInstr *MI); 123 static unsigned getSrcFromCopy(const MachineInstr *MI, argument 128 if (MI->getOpcode() == AArch64::FMOVDXr || 129 MI->getOpcode() == AArch64::FMOVXDr) 130 return MI->getOperand(1).getReg(); 133 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) { 135 return MI->getOperand(1).getReg(); 139 if (MI 174 isTransformable(const MachineInstr *MI) argument 264 insertCopy(const AArch64InstrInfo *TII, MachineInstr *MI, unsigned Dst, unsigned Src, bool IsKill) argument 278 transformInstruction(MachineInstr *MI) argument 357 MachineInstr *MI = I; local [all...] |
H A D | AArch64BranchRelaxation.cpp | 84 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI); 86 bool isBlockInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); 87 bool fixupConditionalBranch(MachineInstr *MI); 89 unsigned getInstrOffset(MachineInstr *MI) const; 167 for (const MachineInstr &MI : MBB) 168 Size += TII->GetInstSizeInBytes(&MI); 175 unsigned AArch64BranchRelaxation::getInstrOffset(MachineInstr *MI) const { 176 MachineBasicBlock *MBB = MI->getParent(); 183 // Sum instructions before MI in MBB. 184 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; 212 splitBlockBeforeInstr(MachineInstr *MI) argument 255 isBlockInRange(MachineInstr *MI, MachineBasicBlock *DestBB, unsigned Bits) argument 291 getDestBlock(MachineInstr *MI) argument 344 invertBccCondition(MachineInstr *MI) argument 354 fixupConditionalBranch(MachineInstr *MI) argument 457 MachineInstr *MI = MBB.getFirstTerminator(); local [all...] |
H A D | AArch64DeadRegisterDefinitionsPass.cpp | 32 bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI); 34 bool usesFrameIndex(const MachineInstr &MI); 52 unsigned Reg, const MachineInstr &MI) { 53 for (const MachineOperand &MO : MI.implicit_operands()) 60 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) { argument 61 for (const MachineOperand &Op : MI.uses()) 70 for (MachineInstr &MI : MBB) { 71 if (usesFrameIndex(MI)) { 78 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { 79 MachineOperand &MO = MI 51 implicitlyDefinesOverlappingReg( unsigned Reg, const MachineInstr &MI) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 18 void printInstruction(const MCInst *MI, raw_ostream &O); 22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); 25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O); 27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.h | 34 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; 35 bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS); 39 void printInstruction(const MCInst *MI, raw_ostream &O); 40 bool printAliasInstr(const MCInst *MI, raw_ostream &O); 41 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 45 void printOperand(const MCInst *MI, int opNum, raw_ostream &OS); 46 void printMemOperand(const MCInst *MI, int opNum, raw_ostream &OS, 48 void printCCOperand(const MCInst *MI, int opNum, raw_ostream &OS); 49 bool printGetPCX(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.h | 21 void EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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H A D | X86ATTInstPrinter.cpp | 43 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 45 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 52 if (!printAliasInstr(MI, OS)) 53 printInstruction(MI, OS); 60 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 63 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 65 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 87 void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, argument 89 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 127 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigne argument 141 printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 162 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 184 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument 230 printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument 249 printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument 260 printMemOffset(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
H A D | X86IntelInstPrinter.cpp | 35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 37 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 43 printInstruction(MI, OS); 50 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 53 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 55 int64_t Imm = MI->getOperand(Op).getImm() & 0xf; 77 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op, argument 79 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f; 117 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, argument 119 int64_t Imm = MI 130 printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 151 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 164 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument 216 printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument 230 printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O) argument 238 printMemOffset(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 18 void printInstruction(const MCInst *MI, raw_ostream &O); 22 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); 25 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 26 // void printUnsignedImm(const MCInst *MI, int OpNo, raw_ostream &O); 27 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcCodeEmitter.cpp | 65 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 67 void emitInstruction(MachineBasicBlock::instr_iterator MI, 73 unsigned getMachineOpValue(const MachineInstr &MI, 76 unsigned getCallTargetOpValue(const MachineInstr &MI, 78 unsigned getBranchTargetOpValue(const MachineInstr &MI, 80 unsigned getBranchPredTargetOpValue(const MachineInstr &MI, 82 unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI, 87 unsigned getRelocation(const MachineInstr &MI, 128 void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI, argument 130 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI); 177 getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const argument 195 getCallTargetOpValue(const MachineInstr &MI, unsigned opIdx) const argument 201 getBranchTargetOpValue(const MachineInstr &MI, unsigned opIdx) const argument 207 getBranchPredTargetOpValue(const MachineInstr &MI, unsigned opIdx) const argument 213 getBranchOnRegTargetOpValue(const MachineInstr &MI, unsigned opIdx) const argument 219 getRelocation(const MachineInstr &MI, const MachineOperand &MO) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 47 MachineInstr *MI; member in class:llvm::MachineInstrBuilder 49 MachineInstrBuilder() : MF(nullptr), MI(nullptr) {} 53 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} 57 operator MachineInstr*() const { return MI; } 58 MachineInstr *operator->() const { return MI; } 59 operator MachineBasicBlock::iterator() const { return MI; } 68 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 84 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); 89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); 94 MI 255 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 266 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 294 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 304 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 382 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD); local 436 MachineInstr *MI = B; local 444 MIBundleBuilder(MachineInstr *MI) argument 462 insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI) argument 484 prepend(MachineInstr *MI) argument 490 append(MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 29 void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 31 printInstruction(MI, O); 35 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, argument 37 const MCOperand &Op = MI->getOperand(OpNo); 46 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 49 const MCOperand &Op = MI->getOperand(OpNo); 60 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, argument 63 const MCOperand &Base = MI->getOperand(OpNo); 64 const MCOperand &Disp = MI->getOperand(OpNo+1); 89 void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigne argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { argument 123 if (MI->getOperand(Op).isFI()) return true; 124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() && 125 MI->getOperand(Op+X86::AddrBaseReg).isReg() && 126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && 127 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 128 (MI->getOperand(Op+X86::AddrDisp).isImm() || 129 MI->getOperand(Op+X86::AddrDisp).isGlobal() || 130 MI->getOperand(Op+X86::AddrDisp).isCPI() || 131 MI 134 isMem(const MachineInstr *MI, unsigned Op) argument [all...] |
/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 48 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 51 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 54 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 57 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 60 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 63 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 66 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 69 unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, 72 unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, 75 unsigned get_crbitm_encoding(const MCInst &MI, unsigne 163 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 175 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 188 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 201 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 213 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 225 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 244 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 263 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 279 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 292 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 304 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ExpandSpecialInstrs.cpp | 77 MachineInstr &MI = *I; local 81 if (TII->isLDSRetInstr(MI.getOpcode())) { 82 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 84 MachineOperand &DstOp = MI.getOperand(DstIdx); 88 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), 94 MI.getOperand(LDSPredSelIdx).getReg()); 97 switch (MI.getOpcode()) { 101 uint64_t Flags = MI.getOperand(3).getImm(); 105 MI.getOperand(2).getImm(), // opcode 106 MI [all...] |
H A D | AMDGPUInstrInfo.h | 54 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 57 unsigned isLoadFromStackSlot(const MachineInstr *MI, 59 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 61 bool hasLoadFromStackSlot(const MachineInstr *MI, 64 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 65 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 67 bool hasStoreFromStackSlot(const MachineInstr *MI, 78 MachineBasicBlock::iterator MI, DebugLoc DL, 82 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 85 MachineBasicBlock::iterator MI, [all...] |
H A D | SIInstrInfo.h | 28 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, 34 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, 42 MachineBasicBlock::iterator MI, 56 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const; 66 MachineBasicBlock::iterator MI, DebugLoc DL, 71 MachineBasicBlock::iterator MI, 77 MachineBasicBlock::iterator MI, 82 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const; 86 MachineInstr *commuteInstruction(MachineInstr *MI, 89 bool isTriviallyReMaterializable(const MachineInstr *MI, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 123 MachineBasicBlock::iterator MI, 133 MachineBasicBlock::iterator MI, 142 MachineInstr *MI, 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 141 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 149 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument 157 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 221 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 238 convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 64 void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, argument 66 const MachineOperand &MO = MI->getOperand(OpNo); 109 bool HexagonAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, argument 120 return AsmPrinter::PrintAsmOperand(MI, OpNo, AsmVariant, ExtraCode, OS); 123 printOperand(MI, OpNo, OS); 127 if (!MI->getOperand(OpNo).isReg() || 128 OpNo+1 == MI->getNumOperands() || 129 !MI->getOperand(OpNo+1).isReg()) 136 if (MI->getOperand(OpNo).isImm()) 142 printOperand(MI, OpN 146 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 175 EmitInstruction(const MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 57 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, argument 62 MachineBasicBlock &MBB = *MI->getParent(); 67 DebugLoc DL = MI->getDebugLoc(); 70 int FrameIndex = MI->getOperand(FIOperandNum).getIndex(); 73 MI->getOperand(FIOperandNum + 1).getImm()); 76 if (MI->isDebugValue()) { 77 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false); 78 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 84 unsigned Opcode = MI->getOpcode(); 87 MI [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 123 MachineBasicBlock::iterator MI, 133 MachineBasicBlock::iterator MI, 142 MachineInstr *MI, 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 141 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 149 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument 157 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 221 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 238 convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const argument [all...] |