Searched refs:Opc (Results 26 - 50 of 154) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116 SDValue &Offset, SDValue &Opc);
118 SDValue &Opc) {
119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
123 SDValue &Opc) {
124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
128 SDValue &Opc) {
129 SelectAddrMode2Worker(N, Base, Offset, Opc);
130 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
143 SDValue &Offset, SDValue &Opc);
117 SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
122 SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
127 SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
298 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
467 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument
490 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
569 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
666 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
803 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
839 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
859 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
884 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
934 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
1237 SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, SDValue &Opc) argument
1670 isVLDfixed(unsigned Opc) argument
1697 isVSTfixed(unsigned Opc) argument
1722 getVLDSTRegisterUpdateOpcode(unsigned Opc) argument
1830 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
1980 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
2148 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
2212 unsigned Opc = Opcodes[OpcodeIndex]; local
2252 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument
2290 unsigned Opc = isSigned local
2500 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? local
2569 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) local
2689 unsigned Opc = Subtarget->isThumb() ? local
2716 unsigned Opc = 0; local
2736 unsigned Opc = 0; local
2756 unsigned Opc = 0; local
[all...]
H A DThumb2SizeReduction.cpp334 unsigned Opc = MI->getOpcode(); local
335 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
336 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
337 Opc == ARM::t2LDMDB_UPD);
338 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
354 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc
375 unsigned Opc = Entry.NarrowOpc1; local
529 unsigned Opc = MI->getOpcode(); local
[all...]
H A DThumb2InstrInfo.cpp44 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
268 unsigned Opc = 0;
282 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
283 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
290 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
303 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
307 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
322 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
626 unsigned Opc = MI->getOpcode();
627 if (Opc
[all...]
H A DARMLoadStoreOptimizer.cpp290 static bool isT1i32Load(unsigned Opc) { argument
291 return Opc == ARM::tLDRi;
294 static bool isT2i32Load(unsigned Opc) { argument
295 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
298 static bool isi32Load(unsigned Opc) { argument
299 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ;
302 static bool isT1i32Store(unsigned Opc) { argument
306 isT2i32Store(unsigned Opc) argument
310 isi32Store(unsigned Opc) argument
314 getImmScale(unsigned Opc) argument
343 unsigned Opc = MBBI->getOpcode(); local
904 getUpdatingLSMultipleOpcode(unsigned Opc, ARM_AM::AMSubMode Mode) argument
1069 getPreIndexedLoadStoreOpcode(unsigned Opc, ARM_AM::AddrOpc Mode) argument
1094 getPostIndexedLoadStoreOpcode(unsigned Opc, ARM_AM::AddrOpc Mode) argument
2138 int Opc = MI->getOpcode(); local
[all...]
H A DThumb2InstrInfo.h32 // Return the non-pre/post incrementing version of 'Opc'. Return 0
34 unsigned getUnindexedOpcode(unsigned Opc) const override;
H A DThumb1RegisterInfo.cpp127 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); local
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
130 if (Opc != ARM::tADDhirr)
141 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, argument
146 if (Opc == ARM::tADDrSPi) {
180 int Opc = 0;
188 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
201 Opc = ARM::tADDrSPi;
210 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
215 Opc
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp313 unsigned Opc = 0; local
329 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr;
339 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr;
356 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr;
362 assert(Opc && SrcOpNum && "Missing parameters");
366 return Opc;
494 unsigned Opc = 0; local
499 Opc = AArch64::CSELXr;
503 Opc = AArch64::CSELWr;
507 Opc
839 unsigned Opc = Instr.getOpcode(); local
[all...]
H A DAArch64AdvSIMDScalarPass.cpp160 static int getTransformOpcode(unsigned Opc) { argument
161 switch (Opc) {
171 return Opc;
175 int Opc = MI->getOpcode(); local
176 return Opc != getTransformOpcode(Opc);
H A DAArch64ISelDAGToDAG.cpp140 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
144 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
146 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
148 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
149 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
151 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
152 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
153 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
154 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
209 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc, argument
878 SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt) argument
990 SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1014 SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument
1049 SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1068 SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1124 SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1169 SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1227 SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1260 SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc) argument
1298 isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits, bool BiggerPattern) argument
1384 isOneBitExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB) argument
1428 isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, bool BiggerPattern) argument
1491 isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits = 0, bool BiggerPattern = false) argument
1530 unsigned Opc, LSB, MSB; local
1831 isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Dst, SDValue &Src, unsigned &ImmR, unsigned &ImmS, SelectionDAG *CurDAG) argument
1929 unsigned Opc; local
1947 unsigned Opc; local
[all...]
H A DAArch64FastISel.cpp209 unsigned Opc; local
212 Opc = AArch64::FMOVDi;
215 Opc = AArch64::FMOVSi;
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
234 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui; local
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
522 unsigned Opc; local
533 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
538 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
543 Opc
1131 unsigned Opc; local
1175 unsigned Opc; local
1764 unsigned Opc; local
1900 unsigned Opc; local
[all...]
H A DAArch64LoadStoreOptimizer.cpp113 static bool isUnscaledLdst(unsigned Opc) { argument
114 switch (Opc) {
178 static unsigned getMatchingPairOpcode(unsigned Opc) { argument
179 switch (Opc) {
215 static unsigned getPreIndexedOpcode(unsigned Opc) { argument
216 switch (Opc) {
242 static unsigned getPostIndexedOpcode(unsigned Opc) { argument
243 switch (Opc) {
392 int Opc = FirstMI->getOpcode(); local
394 bool IsUnscaled = isUnscaledLdst(Opc);
837 int Opc = MI->getOpcode(); local
[all...]
H A DAArch64BranchRelaxation.cpp274 static bool isConditionalBranch(unsigned Opc) { argument
275 switch (Opc) {
309 static unsigned getOppositeConditionOpcode(unsigned Opc) { argument
310 switch (Opc) {
325 static unsigned getBranchDisplacementBits(unsigned Opc) { argument
326 switch (Opc) {
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, argument
74 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
80 Cond.push_back(MachineOperand::CreateImm(Opc));
101 unsigned Opc = Cond[0].getImm(); local
102 const MCInstrDesc &MCID = get(Opc);
H A DMips16ISelLowering.h51 MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
1570 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { argument
1582 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
1804 unsigned Opc = 0; local
1809 Opc = AtomicOpcTbl[Op][ConstantI8];
1811 Opc = AtomicOpcTbl[Op][I8];
1816 Opc = AtomicOpcTbl[Op][SextConstantI16];
1818 Opc = AtomicOpcTbl[Op][ConstantI16];
1820 Opc
1926 isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, SDValue StoredVal, SelectionDAG *CurDAG, LoadSDNode* &LoadNode, SDValue &InputChain) argument
2011 getFusedLdStOpcode(EVT &LdVT, unsigned Opc) argument
2029 SelectGather(SDNode *Node, unsigned Opc) argument
2060 unsigned Opc, MOpc; local
2096 unsigned Opc; local
2717 unsigned Opc = StoredVal->getOpcode(); local
[all...]
H A DX86InstrInfo.cpp1814 unsigned Opc = Orig->getOpcode(); local
1815 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1863 unsigned Opc, bool AllowSP,
1869 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1871 RC = Opc != X86::LEA32r ?
1878 if (Opc != X86::LEA64_32r) {
1950 unsigned Opc, leaInReg; local
1952 Opc = X86::LEA64_32r;
1955 Opc = X86::LEA32r;
1973 get(Opc), leaOutRe
1862 classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned Opc, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const argument
2130 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; local
2171 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r local
2202 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r local
2236 unsigned Opc; local
2310 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; local
2369 unsigned Opc; local
2406 unsigned Opc; local
2529 getCondFromSETOpc(unsigned Opc) argument
2552 getCondFromCMovOpc(unsigned Opc) argument
2674 static const uint16_t Opc[16][2] = { local
2701 static const uint16_t Opc[32][3] = { local
2957 unsigned Opc = GetCondBranchFromCond(CC); local
3014 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), local
3108 unsigned Opc = 0; local
3293 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); local
3309 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget); local
3330 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); local
3344 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget); local
4318 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; local
4475 unsigned Opc = LoadMI->getOpcode(); local
4550 unsigned Opc = MI->getOpcode(); local
4587 unsigned Opc = I->second.first; local
4715 unsigned Opc = I->second.first; local
4811 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex) const argument
[all...]
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, argument
410 bool isSub = Opc == sub;
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
493 bool isSub = Opc == sub;
/external/llvm/include/llvm/IR/
H A DInstrTypes.h194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
196 BinaryOperator *BO = Create(Opc, V1, V2, Name);
200 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
202 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
206 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
208 BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
213 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
215 BinaryOperator *BO = Create(Opc, V1, V2, Name);
219 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
221 BinaryOperator *BO = Create(Opc, V
225 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
232 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument
238 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
244 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
[all...]
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp479 vspltisw(const char *N, unsigned Opc)
480 : Operator(MakeMask(Elt, Elt, Elt, Elt), N, Opc) {}
490 vsldoi(const char *Name, unsigned Opc)
491 : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), Name, Opc) {
528 vdup(const char *N, unsigned Opc)
529 : Operator(MakeMask(Elt, Elt, Elt, Elt), N, Opc) {}
539 vext(const char *Name, unsigned Opc)
540 : Operator(MakeMask(N&7, (N+1)&7, (N+2)&7, (N+3)&7), Name, Opc) {
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h741 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs,
743 : NodeType(Opc), OperandsNeedDelete(true), HasDebugValue(false),
758 SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs)
759 : NodeType(Opc), OperandsNeedDelete(false), HasDebugValue(false),
946 UnarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument
948 : SDNode(Opc, Order, dl, VTs) {
958 BinarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument
960 : SDNode(Opc, Order, dl, VTs) {
971 BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, argument
973 : BinarySDNode(Opc, Orde
1000 TernarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, SDValue X, SDValue Y, SDValue Z) argument
1190 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1198 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1207 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, SDValue Chain, SDValue Ptr, MachineMemOperand *MMO, AtomicOrdering Ordering, SynchronizationScope SynchScope) argument
1216 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT MemVT, const SDValue* AllOps, SDUse *DynOps, unsigned NumOps, MachineMemOperand *MMO, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) argument
1272 MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs, ArrayRef<SDValue> Ops, EVT MemoryVT, MachineMemOperand *MMO) argument
1906 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc DL, SDVTList VTs) argument
[all...]
/external/clang/include/clang/AST/
H A DExpr.h1663 unsigned Opc : 5;
1676 Opc(opc), Loc(l), Val(input) {}
1680 : Expr(UnaryOperatorClass, Empty), Opc(UO_AddrOf) { }
1682 Opcode getOpcode() const { return static_cast<Opcode>(Opc); }
1683 void setOpcode(Opcode O) { Opc = O; }
1739 static OverloadedOperatorKind getOverloadedOperator(Opcode Opc);
2917 unsigned Opc : 6;
2940 Opc(opc), FPContractable(fpContractable), OpLoc(opLoc) {
2949 : Expr(BinaryOperatorClass, Empty), Opc(BO_Comma) { }
2955 Opcode getOpcode() const { return static_cast<Opcode>(Opc); }
2987 isAdditiveOp(Opcode Opc) argument
2989 isShiftOp(Opcode Opc) argument
2992 isBitwiseOp(Opcode Opc) argument
2995 isRelationalOp(Opcode Opc) argument
2998 isEqualityOp(Opcode Opc) argument
3001 isComparisonOp(Opcode Opc) argument
3004 negateComparisonOp(Opcode Opc) argument
3017 reverseComparisonOp(Opcode Opc) argument
3031 isLogicalOp(Opcode Opc) argument
3034 isAssignmentOp(Opcode Opc) argument
3039 isCompoundAssignmentOp(Opcode Opc) argument
3045 getOpForCompoundAssignment(Opcode Opc) argument
3053 isShiftAssignOp(Opcode Opc) argument
[all...]
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp466 unsigned Opc = Node->getMachineOpcode();
481 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
521 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
522 Opc == TargetOpcode::SUBREG_TO_REG) {
551 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
555 if (Opc == TargetOpcode::SUBREG_TO_REG) {
710 unsigned Opc = Node->getMachineOpcode();
713 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
714 Opc == TargetOpcode::INSERT_SUBREG ||
715 Opc
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp559 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? local
568 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
740 unsigned Opc = Op.getOpcode(); local
747 switch (Opc) {
767 if (Opc == ISD::SRL && ShiftAmount) {
775 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
1204 unsigned Opc; local
1209 Opc = MSP430::SHL8r1;
1213 Opc = MSP430::SHL16r1;
1217 Opc
1306 unsigned Opc = MI->getOpcode(); local
[all...]
H A DMSP430InstrInfo.cpp95 unsigned Opc; local
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp590 unsigned Opc = I->getOpcode(); local
591 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
652 unsigned Opc = MII->getOpcode(); local
653 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
654 Opc == PPC::BDZ8 || Opc == PPC::BDZ)

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