Searched refs:Opc (Results 76 - 100 of 154) sorted by relevance

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/external/llvm/lib/IR/
H A DAutoUpgrade.cpp524 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, argument
526 if (Opc != Instruction::BitCast)
546 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { argument
547 if (Opc != Instruction::BitCast)
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h37 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc dl,
H A DMipsConstantIslandPass.cpp683 int Opc = I->getOpcode(); local
688 int UOpc = Opc;
689 switch (Opc) {
756 if (Opc == Mips::CONSTPOOL_ENTRY)
774 switch (Opc) {
1183 static inline unsigned getUnconditionalBrDisp(int Opc) { argument
1184 switch (Opc) {
H A DMipsSEISelLowering.cpp68 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
69 setOperationAction(Opc, VecTys[i], Expand);
247 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
248 setOperationAction(Opc, Ty, Expand);
296 for (unsigned Opc = 0; Opc < IS
844 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget *Subtarget) argument
1307 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1356 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1438 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
[all...]
/external/llvm/lib/Target/R600/
H A DAMDGPUInstrInfo.h120 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp180 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, argument
H A DAMDGPUInstrInfo.h106 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
H A DAMDILISelDAGToDAG.cpp155 unsigned int Opc = N->getOpcode(); local
159 switch (Opc) {
/external/llvm/include/llvm/Analysis/
H A DTargetFolder.h109 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
111 return Fold(ConstantExpr::get(Opc, LHS, RHS));
/external/llvm/include/llvm/IR/
H A DConstantFolder.h97 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
99 return ConstantExpr::get(Opc, LHS, RHS);
H A DNoFolder.h147 Instruction *CreateBinOp(Instruction::BinaryOps Opc, argument
149 return BinaryOperator::Create(Opc, LHS, RHS);
/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp142 unsigned Opc = PI->getOpcode(); local
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
H A DMSP430ISelDAGToDAG.cpp366 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); local
371 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h75 CondCode getCondFromCMovOpc(unsigned Opc);
336 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
H A DX86RegisterInfo.cpp480 unsigned Opc = MI.getOpcode(); local
481 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
506 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1886 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
1887 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
1891 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
1892 Opc == TargetOpcode::SUBREG_TO_REG ||
1893 Opc == TargetOpcode::INSERT_SUBREG)
2110 unsigned Opc = N->getMachineOpcode();
2111 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
2112 Opc == TargetOpcode::INSERT_SUBREG ||
2113 Opc
[all...]
H A DScheduleDAGSDNodes.cpp304 unsigned Opc = Node->getMachineOpcode();
305 const MCInstrDesc &MCID = TII->get(Opc);
439 unsigned Opc = MainNode->getMachineOpcode();
440 const MCInstrDesc &MCID = TII->get(Opc);
/external/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp1007 unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri; local
1008 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1013 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
1015 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1023 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1146 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; local
1147 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1652 unsigned Opc = Old->getOpcode(); local
1656 if (Opc
[all...]
H A DARMISelLowering.cpp3213 unsigned Opc = Cmp.getOpcode(); local
3215 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3216 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3218 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3220 Opc = Cmp.getOpcode();
3221 if (Opc == ARMISD::CMPFP)
3222 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3224 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3225 Cmp = DAG.getNode(Opc, D
3302 unsigned Opc = Cond.getOpcode(); local
3733 unsigned Opc; local
3764 unsigned Opc; local
3787 unsigned Opc; local
4012 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; local
4271 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; local
4285 unsigned Opc = 0; local
6060 unsigned Opc; local
7867 unsigned Opc = MULOp->getOpcode(); local
9455 unsigned Opc = 0; local
9684 isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const argument
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1091 unsigned Opc = 0; local
1096 Opc = AArch64ISD::ADDS;
1100 Opc = AArch64ISD::ADDS;
1104 Opc = AArch64ISD::SUBS;
1108 Opc = AArch64ISD::SUBS;
1186 if (Opc) {
1190 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1274 unsigned Opc; local
1280 Opc = AArch64ISD::ADDS;
1283 Opc
2856 unsigned Opc = LHS.getOpcode(); local
3180 unsigned Opc = CC.getOpcode(); local
3707 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; local
4794 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; local
4798 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; local
4802 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; local
4807 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2; local
4811 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2; local
4815 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2; local
5804 unsigned Opc = local
5813 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp734 unsigned Opc; local
736 Opc = PPC::OR;
738 Opc = PPC::OR8;
740 Opc = PPC::FMR;
742 Opc = PPC::MCRF;
744 Opc = PPC::VOR;
754 Opc = PPC::XXLOR;
756 Opc = PPC::XXLORf;
758 Opc = PPC::CROR;
762 const MCInstrDesc &MCID = get(Opc);
1284 unsigned Opc = MI->getOpcode(); local
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDILISelDAGToDAG.cpp155 unsigned int Opc = N->getOpcode(); local
159 switch (Opc) {
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp176 unsigned Opc = I->getOpcode(); local
177 switch (Opc) {
191 Res = BinaryOperator::Create((Instruction::BinaryOps)Opc, LHS, RHS);
206 Opc == Instruction::SExt);
358 unsigned Opc = I->getOpcode(); local
359 switch (Opc) {
671 unsigned Opc = I->getOpcode(), Tmp; local
672 switch (Opc) {
693 (Opc == Instruction::And || Opc
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp820 unsigned Opc = NVPTXISD::StoreParamV2; local
838 Opc = NVPTXISD::StoreParamV4;
863 Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1145 unsigned Opc = NVPTXISD::LoadParamV4;
1148 Opc = NVPTXISD::LoadParamV2;
1172 Opc, dl, DAG.getVTList(LoadRetVTs),
1292 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; local
1301 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1325 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1329 SDValue Hi = DAG.getNode(Opc, d
2015 unsigned Opc = NVPTXISD::StoreRetvalV2; local
2990 unsigned Opc; local
[all...]
/external/llvm/lib/MC/
H A DMCExpr.cpp137 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS, argument
139 return new (Ctx) MCBinaryExpr(Opc, LHS, RHS);
142 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr, argument
144 return new (Ctx) MCUnaryExpr(Opc, Expr);

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