Searched refs:Reg (Results 276 - 300 of 321) sorted by relevance

<<111213

/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp75 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
78 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
79 return SelectShiftedRegister(N, false, Reg, Shift);
81 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) { argument
82 return SelectShiftedRegister(N, true, Reg, Shift);
165 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
319 SDValue &Reg, SDValue &Shift) {
331 Reg = N.getOperand(0);
535 bool AArch64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg, argument
552 Reg
318 SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg, SDValue &Shift) argument
[all...]
H A DAArch64CollectLOH.cpp331 unsigned Reg = Entry.second; local
338 BBGen[Reg] = ADRPMode ? &MI : nullptr;
339 BBKillSet.set(Reg);
490 DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
1013 DEBUG(assert(IdToReg[CurRegId] == CurRegId && "Reg index mismatches"));
1035 "Reg index mismatches insertion index."));
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp64 unsigned Reg; member in union:__anon25970::Address::__anon25972
73 Base.Reg = 0;
853 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
854 return Addr.Base.Reg != 0;
897 Addr.Base.Reg = ResultReg;
904 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
943 MIB.addReg(Addr.Base.Reg);
2006 Addr.Base.Reg
2095 unsigned Reg = getRegForValue(RV); local
[all...]
H A DThumb1RegisterInfo.cpp509 unsigned Reg) const {
519 .addReg(Reg, RegState::Kill));
548 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
H A DARMCodeEmitter.cpp253 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
259 Binary |= (Reg << 13);
291 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); local
309 Binary |= (Reg << 13);
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp91 unsigned getHWRegIndexGen(unsigned int Reg) const;
95 unsigned getHWRegChanGen(unsigned int Reg) const;
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp367 unsigned Reg = dstClass->getRegister(SGPRIndex); local
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfUnit.h362 void addRegisterOp(DIELoc &TheDie, unsigned Reg);
365 void addRegisterOffset(DIELoc &TheDie, unsigned Reg, int64_t Offset);
H A DDwarfUnit.cpp494 void DwarfUnit::addRegisterOp(DIELoc &TheDie, unsigned Reg) { argument
496 int DWReg = RI->getDwarfRegNum(Reg, false);
502 for (MCSuperRegIterator SR(Reg, RI); SR.isValid() && DWReg < 0; ++SR) {
505 Idx = RI->getSubRegIndex(*SR, Reg);
539 void DwarfUnit::addRegisterOffset(DIELoc &TheDie, unsigned Reg,
542 unsigned DWReg = RI->getDwarfRegNum(Reg, false);
544 if (Reg == TRI->getFrameRegister(*Asm->MF))
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp504 unsigned Reg = MO.getReg();
505 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp663 unsigned NVPTXAsmPrinter::encodeVirtualRegister(unsigned Reg) { argument
664 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
665 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
668 unsigned RegNum = RegMap[Reg];
695 return Reg & 0x0FFFFFFF;
894 NVPTXAsmPrinter::getVirtualRegisterName(unsigned Reg) const {
895 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
904 VRegMap::const_iterator VI = RegMap.find(Reg);
H A DNVPTXAsmPrinter.h209 unsigned encodeVirtualRegister(unsigned Reg);
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp235 const CodeGenRegister *Reg = getRegBank().getReg(R); local
240 if (RC.contains(Reg)) {
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp91 unsigned getHWRegIndexGen(unsigned int Reg) const;
95 unsigned getHWRegChanGen(unsigned int Reg) const;
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIISelLowering.cpp367 unsigned Reg = dstClass->getRegister(SGPRIndex); local
369 DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp795 unsigned Reg = VA.getLocReg(); local
796 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
998 unsigned Reg = VA.getLocReg(); local
999 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1001 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
2606 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); local
2607 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2609 return Reg;
3241 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); local
3248 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); local
[all...]
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h324 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
/external/valgrind/main/VEX/priv/
H A Dhost_ppc_defs.h204 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
252 } Reg; member in union:__anon31981::__anon31982
278 HReg Reg; member in union:__anon31986::__anon31987
304 HReg Reg; member in union:__anon31989::__anon31990
H A Dhost_ppc_defs.c411 op->Prh.Reg.reg = reg;
424 ppHRegPPC(op->Prh.Reg.reg);
439 addHRegUse(u, HRmRead, op->Prh.Reg.reg);
451 op->Prh.Reg.reg = lookupHRegRemap(m, op->Prh.Reg.reg);
470 op->Pri.Reg = reg;
480 ppHRegPPC(dst->Pri.Reg);
495 addHRegUse(u, HRmRead, dst->Pri.Reg);
507 dst->Pri.Reg = lookupHRegRemap(m, dst->Pri.Reg);
[all...]
/external/llvm/lib/CodeGen/
H A DMachineScheduler.cpp938 unsigned Reg = LiveUses[LUIdx]; local
939 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
940 if (!TRI->isVirtualRegister(Reg))
947 const LiveInterval &LI = LIS->getInterval(Reg);
960 UI = VRegUses.find(Reg); UI != VRegUses.end(); ++UI) {
970 getPressureDiff(SU).addPressureChange(Reg, true, &MRI);
1116 unsigned Reg = *RI; local
1117 if (!TRI->isVirtualRegister(Reg))
1119 const LiveInterval &LI = LIS->getInterval(Reg);
1133 UI = VRegUses.find(Reg); U
[all...]
/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp598 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
599 MFI->LiveOuts.push_back(Reg);
600 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
631 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local
634 MRI.addLiveIn(Reg);
636 SDLoc(DAG.getEntryNode()), Reg, VT);
1683 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); local
1684 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2106 if (RegisterSDNode *Reg =
2108 if (Reg
[all...]
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp419 void onRegister(unsigned Reg) { argument
428 TmpReg = Reg;
436 IndexReg = Reg;
2160 static bool convertToSExti8(MCInst &Inst, unsigned Opcode, unsigned Reg, argument
2165 TmpInst.addOperand(MCOperand::CreateReg(Reg));
2166 TmpInst.addOperand(MCOperand::CreateReg(Reg));
/external/llvm/include/llvm/MC/
H A DMCStreamer.h125 virtual void emitMovSP(unsigned Reg, int64_t Offset = 0);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp731 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, local
733 return std::make_pair(true, Reg.getNode());
/external/clang/lib/StaticAnalyzer/Core/
H A DExprEngine.cpp226 SVal Reg = loc::MemRegionVal(TR); local
231 State = State->bindLoc(Reg, V);
237 Reg = StoreMgr.evalDerivedToBase(Reg, *I);
240 State = State->BindExpr(Result, LC, Reg);

Completed in 400 milliseconds

<<111213