Searched refs:TM (Results 101 - 125 of 414) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DLLVMTargetMachine.cpp84 static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM, argument
91 TM->addAnalysisPasses(PM);
95 TargetPassConfig *PassConfig = TM->createPassConfig(PM);
114 new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
115 &TM->getTargetLowering()->getObjFileLowering());
119 PM.add(new MachineFunctionAnalysis(*TM));
123 (TM->getOptLevel() == CodeGenOpt::None &&
125 TM->setFastISel(true);
H A DTargetLoweringObjectFileImpl.cpp48 const GlobalValue *GV, Mangler &Mang, const TargetMachine &TM,
53 TM.getSymbol(GV, Mang)->getName());
55 return TM.getSymbol(GV, Mang);
60 const TargetMachine &TM,
75 unsigned Size = TM.getDataLayout()->getPointerSize();
77 Streamer.EmitValueToAlignment(TM.getDataLayout()->getPointerABIAlignment());
88 const TargetMachine &TM, MachineModuleInfo *MMI,
94 MCSymbol *SSym = getSymbolWithGlobalValueBase(GV, ".DW.stub", Mang, TM);
100 MCSymbol *Sym = TM.getSymbol(GV, Mang);
110 getTTypeGlobalReference(GV, Encoding, Mang, TM, MM
47 getCFIPersonalitySymbol( const GlobalValue *GV, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI) const argument
59 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument
86 getTTypeGlobalReference( const GlobalValue *GV, unsigned Encoding, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI, MCStreamer &Streamer) const argument
672 getTTypeGlobalReference( const GlobalValue *GV, unsigned Encoding, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI, MCStreamer &Streamer) const argument
704 getCFIPersonalitySymbol( const GlobalValue *GV, Mangler &Mang, const TargetMachine &TM, MachineModuleInfo *MMI) const argument
[all...]
H A DGlobalMerge.cpp95 const TargetMachine *TM; member in class:__anon25749::GlobalMerge
119 explicit GlobalMerge(const TargetMachine *TM = nullptr)
120 : FunctionPass(ID), TM(TM) {
145 const TargetLowering *TLI = TM->getTargetLowering();
284 const TargetLowering *TLI = TM->getTargetLowering();
322 if (TargetLoweringObjectFile::getKindForGlobal(I, *TM).isBSSLocal())
359 Pass *llvm::createGlobalMergePass(const TargetMachine *TM) { argument
360 return new GlobalMerge(TM);
/external/llvm/lib/Target/AArch64/
H A DAArch64CleanupLocalDynamicTLSPass.cpp95 const AArch64TargetMachine *TM = local
97 const AArch64InstrInfo *TII = TM->getInstrInfo();
115 const AArch64TargetMachine *TM = local
117 const AArch64InstrInfo *TII = TM->getInstrInfo();
/external/llvm/lib/Target/Mips/
H A DMipsFrameLowering.h31 static const MipsFrameLowering *create(MipsTargetMachine &TM,
H A DMipsISelDAGToDAG.h34 explicit MipsDAGToDAGISel(MipsTargetMachine &TM) argument
35 : SelectionDAGISel(TM), Subtarget(&TM.getSubtarget<MipsSubtarget>()) {}
131 FunctionPass *createMipsISelDag(MipsTargetMachine &TM);
H A DMipsFrameLowering.cpp85 const MipsFrameLowering *MipsFrameLowering::create(MipsTargetMachine &TM, argument
87 if (TM.getSubtargetImpl()->inMips16Mode())
H A DMipsISelDAGToDAG.cpp50 Subtarget = &TM.getSubtarget<MipsSubtarget>();
236 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) { argument
237 if (TM.getSubtargetImpl()->inMips16Mode())
238 return llvm::createMips16ISelDag(TM);
240 return llvm::createMipsSEISelDag(TM);
H A DMipsLongBranch.cpp65 : MachineFunctionPass(ID), TM(tm),
66 IsPIC(TM.getRelocationModel() == Reloc::PIC_),
67 ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
69 (!TM.getSubtarget<MipsSubtarget>().isTargetNaCl() ? 9 : 10))) {}
85 const TargetMachine &TM; member in class:__anon26053::MipsLongBranch
173 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
189 TM.getRelocationModel() == Reloc::PIC_)))
220 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
257 static_cast<const MipsInstrInfo*>(TM.getInstrInfo());
273 const MipsSubtarget &Subtarget = TM
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/external/mesa3d/src/gallium/drivers/radeon/
H A DR600RegisterInfo.h27 AMDGPUTargetMachine &TM; member in struct:llvm::R600RegisterInfo
H A DSIInstrInfo.h26 AMDGPUTargetMachine &TM; member in class:llvm::SIInstrInfo
H A DSIRegisterInfo.cpp23 TM(tm),
/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp75 const TargetMachine &TM)
78 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
74 HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS, const TargetMachine &TM) argument
H A DHexagonCFGOptimizer.cpp47 HexagonCFGOptimizer(const HexagonTargetMachine& TM) argument
48 : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
251 FunctionPass *llvm::createHexagonCFGOptimizer(const HexagonTargetMachine &TM) { argument
252 return new HexagonCFGOptimizer(TM);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp57 const std::string &FS, const TargetMachine &TM,
62 TLInfo((NVPTXTargetMachine &)TM), TSInfo(&DL), FrameLowering(*this) {
56 NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool is64Bit) argument
/external/llvm/lib/Target/Sparc/
H A DSparcSubtarget.cpp79 const std::string &FS, TargetMachine &TM,
83 InstrInfo(*this), TLInfo(TM), TSInfo(DL), FrameLowering(*this) {}
78 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) argument
H A DSparcCodeEmitter.cpp38 TargetMachine &TM; member in class:__anon26139::SparcCodeEmitter
53 TM(tm), MCE(mce), MCPEs(nullptr),
54 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
106 Subtarget = &TM.getSubtarget<SparcSubtarget> ();
180 return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
275 FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM, argument
277 return new SparcCodeEmitter(TM, JCE);
/external/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.cpp43 const TargetMachine &TM)
52 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
40 SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) argument
H A DSystemZTargetMachine.cpp36 SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM) argument
37 : TargetPassConfig(TM, PM) {}
/external/llvm/lib/Target/X86/
H A DX86AtomicExpandPass.cpp32 const X86TargetMachine *TM; member in class:__anon26184::X86AtomicExpandPass
35 explicit X86AtomicExpandPass(const X86TargetMachine *TM) argument
36 : FunctionPass(ID), TM(TM) {}
68 FunctionPass *llvm::createX86AtomicExpandPass(const X86TargetMachine *TM) { argument
69 return new X86AtomicExpandPass(TM);
106 const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
121 const X86Subtarget &Subtarget = TM->getSubtarget<X86Subtarget>();
/external/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp37 XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM) argument
38 : TargetPassConfig(TM, PM) {}
/external/llvm/test/Bindings/Ocaml/
H A Dtarget.ml84 let module TM = TargetMachine in
85 assert_equal (TM.target machine) target;
86 assert_equal (TM.triple machine) (Target.default_triple ());
87 assert_equal (TM.cpu machine) "";
88 assert_equal (TM.features machine) "";
89 ignore (TM.data_layout machine);
90 TM.set_verbose_asm true machine
/external/llvm/lib/Target/R600/
H A DAMDGPUMCInstLower.cpp91 if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
115 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
116 *TM.getRegisterInfo());
127 TM.getSubtarget<MCSubtargetInfo>());
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp136 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM) argument
137 : TargetPassConfig(TM, PM) {}
161 addPass(createAtomicExpandLoadLinkedPass(TM));
168 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
175 if (TM->getOptLevel() != CodeGenOpt::None)
176 addPass(createGlobalMergePass(TM));
186 TM->Options.EnableFastISel)
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DSIAssignInterpRegs.cpp36 TargetMachine &TM; member in class:__anon13916::SIAssignInterpRegsPass
43 MachineFunctionPass(ID), TM(tm) { }
126 const TargetInstrInfo * TII = TM.getInstrInfo();

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