Searched refs:getOperand (Results 126 - 150 of 529) sorted by relevance

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/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineLoadStoreAlloca.cpp39 return pointsToConstantGlobal(CE->getOperand(0));
297 User *CI = cast<User>(LI.getOperand(0));
298 Value *CastOp = CI->getOperand(0);
361 Value *Op = LI.getOperand(0);
395 const Value *GEPI0 = GEPI->getOperand(0);
440 if (isSafeToLoadUnconditionally(SI->getOperand(1), SI, Align, DL) &&
441 isSafeToLoadUnconditionally(SI->getOperand(2), SI, Align, DL)) {
442 LoadInst *V1 = Builder->CreateLoad(SI->getOperand(1),
443 SI->getOperand(1)->getName()+".val");
444 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(
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H A DInstCombineMulDivRem.cpp50 if (I->isLogicalShift() && isKnownToBeAPowerOfTwo(I->getOperand(0))) {
53 if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC)) {
121 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
232 (BO->getOperand(1) == Op1C || BO->getOperand(1) == Neg) &&
235 Value *Op0BO = BO->getOperand(0), *Op1BO = BO->getOperand(1);
325 if (match(I->getOperand(0), m_SpecificFP(0.5)))
326 Y = I->getOperand(
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/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp470 unsigned SuperReg = MI->getOperand(0).getReg();
476 .addOperand(MI->getOperand(1));
495 unsigned DestReg = MI->getOperand(0).getReg();
498 .addReg(MI->getOperand(1).getReg())
500 .addReg(MI->getOperand(2).getReg())
515 MIB.addOperand(MI->getOperand(i));
529 MI->getOperand(0).getReg())
530 .addReg(MI->getOperand(1).getReg())
544 MI->getOperand(0).getReg())
545 .addReg(MI->getOperand(
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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp352 SDValue Chain = Op.getOperand(0);
353 SDValue Table = Op.getOperand(1);
354 SDValue Index = Op.getOperand(2);
446 isWordAligned(BasePtr->getOperand(0), DAG)) {
447 SDValue NewBasePtr = BasePtr->getOperand(0);
448 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
566 SDValue LHS = Op.getOperand(0);
567 SDValue RHS = Op.getOperand(1);
583 SDValue LHS = Op.getOperand(0);
584 SDValue RHS = Op.getOperand(
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/external/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp119 MachineOperand &TexHandle = MI.getOperand(4);
120 MachineOperand &SampHandle = MI.getOperand(5);
143 MachineOperand &SurfHandle = MI.getOperand(1);
165 MachineOperand &SurfHandle = MI.getOperand(2);
187 MachineOperand &SurfHandle = MI.getOperand(4);
284 MachineOperand &SurfHandle = MI.getOperand(0);
305 MachineOperand &Handle = MI.getOperand(1);
327 assert(TexHandleDef.getOperand(6).isSymbol() && "Load is not a symbol!");
328 StringRef Sym = TexHandleDef.getOperand(6).getSymbolName();
343 assert(TexHandleDef.getOperand(
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H A DNVPTXutil.cpp25 if (MI->getOperand(2).isImm() == false)
27 if (MI->getOperand(2).getImm() != NVPTX::PTXLdStInstCode::PARAM)
/external/llvm/lib/Target/PowerPC/
H A DPPCAsmPrinter.cpp146 const MachineOperand &MO = MI->getOperand(OpNo);
233 if (!MI->getOperand(OpNo).isReg() ||
235 !MI->getOperand(OpNo+1).isReg())
242 if (MI->getOperand(OpNo).isImm())
276 assert(MI->getOperand(OpNo).isReg());
342 const MachineOperand &MO = MI->getOperand(1);
359 TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
373 const MachineOperand &MO = MI->getOperand(2);
402 TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
414 const MachineOperand &MO = MI->getOperand(
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/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp86 if (MI->getOperand(2).isFI() &&
87 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
110 if (MI->getOperand(2).isFI() &&
111 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
112 FrameIndex = MI->getOperand(0).getIndex();
113 return MI->getOperand(
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H A DHexagonExpandPredSpillCode.cpp88 unsigned FP = MI->getOperand(0).getReg();
91 assert(MI->getOperand(1).isImm() && "Not an offset");
92 int Offset = MI->getOperand(1).getImm();
93 int SrcReg = MI->getOperand(2).getReg();
132 int DstReg = MI->getOperand(0).getReg();
135 unsigned FP = MI->getOperand(1).getReg();
138 assert(MI->getOperand(2).isImm() && "Not an offset");
139 int Offset = MI->getOperand(2).getImm();
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp181 Target = Addr.getOperand(0);
418 N = N.getOperand(0);
422 SDValue Op0 = N.getOperand(0);
423 SDValue Op1 = N.getOperand(1);
444 SDValue Full = N.getOperand(0);
445 SDValue Base = N.getOperand(1);
446 SDValue Anchor = Base.getOperand(0);
654 auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
658 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
668 CurDAG->computeKnownBits(Op.getOperand(
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H A DSystemZShortenInst.cpp78 unsigned Reg = MI.getOperand(0).getReg();
85 uint64_t Imm = MI.getOperand(1).getImm();
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
94 MI.getOperand(1).setImm(Imm >> 16);
/external/llvm/include/llvm/Analysis/
H A DConstantsScanner.h35 return isa<Constant>(InstI->getOperand(OpIdx));
56 return cast<Constant>(InstI->getOperand(OpIdx));
/external/llvm/lib/MC/
H A DMCInst.cpp46 getOperand(i).print(OS, MAI);
62 getOperand(i).print(OS, MAI);
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp79 BB = Inst->getOperand(NumOp-1).getMBB();
83 Cond.push_back(Inst->getOperand(i));
227 TBB = LastInst->getOperand(0).getMBB();
250 TBB = SecondLastInst->getOperand(0).getMBB();
262 FBB = LastInst->getOperand(0).getMBB();
274 const char *AsmStr = MI->getOperand(0).getSymbolName();
280 return MI->getOperand(2).getImm();
291 MIB.addOperand(I->getOperand(J));
H A DMipsMCInstLower.cpp169 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
172 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
173 MI->getOperand(2).getMBB(),
184 const MachineOperand &MO = MI->getOperand(I);
189 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
190 MI->getOperand(3).getMBB(), Kind));
206 unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
226 const MachineOperand &MO = MI->getOperand(i);
/external/llvm/unittests/IR/
H A DUserTest.cpp90 EXPECT_EQ(P.getOperand(3), *I);
92 EXPECT_EQ(P.getOperand(6), I[2]);
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp166 const MCOperand &MO = MI.getOperand(OpNo);
178 const MCOperand &MO = MI.getOperand(OpNo);
191 const MCOperand &MO = MI.getOperand(OpNo);
204 const MCOperand &MO = MI.getOperand(OpNo);
216 const MCOperand &MO = MI.getOperand(OpNo);
230 assert(MI.getOperand(OpNo+1).isReg());
231 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16;
233 const MCOperand &MO = MI.getOperand(OpNo);
249 assert(MI.getOperand(OpNo+1).isReg());
250 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpN
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/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp43 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
67 Target = LastInst->getOperand(1).getMBB();
68 Cond.push_back(LastInst->getOperand(0));
74 Target = LastInst->getOperand(1).getMBB();
77 Cond.push_back(LastInst->getOperand(0));
83 Target = LastInst->getOperand(2).getMBB();
86 Cond.push_back(LastInst->getOperand(0));
87 Cond.push_back(LastInst->getOperand(1));
117 TBB = LastInst->getOperand(0).getMBB();
141 TBB = LastInst->getOperand(
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H A DAArch64ISelLowering.cpp576 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
577 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
583 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
600 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
610 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
783 unsigned DestReg = MI->getOperand(0).getReg();
784 unsigned IfTrueReg = MI->getOperand(1).getReg();
785 unsigned IfFalseReg = MI->getOperand(2).getReg();
786 unsigned CondCode = MI->getOperand(3).getImm();
787 bool NZCVKilled = MI->getOperand(
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/external/llvm/lib/Target/ARM/
H A DARMCodeEmitter.cpp155 return getMachineOpValue(MI, MI.getOperand(OpIdx));
247 const MachineOperand &MO = MI.getOperand(Op);
248 const MachineOperand &MO1 = MI.getOperand(Op + 1);
285 const MachineOperand &MO = MI.getOperand(Op);
286 const MachineOperand &MO1 = MI.getOperand(Op + 1);
623 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
624 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
686 const MachineOperand &MO0 = MI.getOperand(0);
687 const MachineOperand &MO1 = MI.getOperand(1);
722 const MachineOperand &MO0 = MI.getOperand(
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/external/llvm/lib/Analysis/
H A DValueTracking.cpp200 ConstantInt *Lower = cast<ConstantInt>(Ranges.getOperand(2*i + 0));
201 ConstantInt *Upper = cast<ConstantInt>(Ranges.getOperand(2*i + 1));
346 computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
347 computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
356 computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
357 computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
366 computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
367 computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
378 computeKnownBitsMul(I->getOperand(0), I->getOperand(
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/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h123 if (MI->getOperand(Op).isFI()) return true;
125 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
127 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
128 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
129 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
130 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
131 MI->getOperand(Op+X86::AddrDisp).isJTI());
135 if (MI->getOperand(Op).isFI()) return true;
137 MI->getOperand(O
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H A DX86CodeEmitter.cpp181 const MachineOperand& MO = MI.getOperand(i);
191 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
195 const MachineOperand& MO = MI.getOperand(i);
202 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
207 const MachineOperand& MO = MI.getOperand(i);
224 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
228 const MachineOperand& MO = MI.getOperand(i);
238 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0)))
242 const MachineOperand& MO = MI.getOperand(i);
452 const MachineOperand &Op3 = MI.getOperand(O
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/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp648 TmpInst.addOperand(Inst.getOperand(0));
649 TmpInst.addOperand(Inst.getOperand(2));
650 TmpInst.addOperand(Inst.getOperand(1));
656 int64_t N = Inst.getOperand(2).getImm();
658 TmpInst.addOperand(Inst.getOperand(0));
659 TmpInst.addOperand(Inst.getOperand(1));
666 int64_t N = Inst.getOperand(2).getImm();
668 TmpInst.addOperand(Inst.getOperand(0));
669 TmpInst.addOperand(Inst.getOperand(1));
676 int64_t N = Inst.getOperand(
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/external/llvm/lib/CodeGen/
H A DMachineInstr.cpp520 TBAAInfo->getOperand(0)->printAsOperand(OS, /*PrintType=*/false);
577 addOperand(MF, MI.getOperand(i));
644 // This is unusual: MI->addOperand(MI->getOperand(i)).
813 const MachineOperand &MO = getOperand(i);
814 const MachineOperand &OMO = Other->getOperand(i);
881 const MachineOperand &MO = getOperand(i);
926 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
935 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
952 const MachineOperand &FlagMO = getOperand(i);
979 if (!getOperand(OpId
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