Searched refs:isReg (Results 51 - 75 of 180) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h299 if (MI.getOperand(i).isReg() &&
566 if (MI.getOperand(i).isReg() &&
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDbgValueHistoryCalculator.cpp32 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
119 if (!MO.isReg() || !MO.isDef() || !MO.getReg())
/external/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp218 Def->getOperand(DefIdx).isReg() &&
506 if (!MO.isReg() || !MO.getReg())
537 assert(MODef.isReg() && "Copies must be between registers.");
649 if (!MO.isReg() || MO.isDef())
745 if (!MOp.isReg())
821 if (!MO.isReg() || !MO.getReg())
863 assert(Def->getOperand(OpIdx).isReg() &&
1010 assert(MO.isReg() && !MO.isDef() && "Source is invalid");
H A DTargetInstrInfo.cpp125 if (HasDef && !MI->getOperand(0).isReg())
134 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
193 if (!MI->getOperand(SrcOpIdx1).isReg() ||
194 !MI->getOperand(SrcOpIdx2).isReg())
228 if (MO.isReg()) {
569 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
607 if (!MO.isReg()) continue;
H A DTargetSchedule.cpp132 if (MO.isReg() && MO.isDef())
148 if (MO.isReg() && MO.readsReg())
H A DCriticalAntiDepBreaker.cpp179 if (!MO.isReg()) continue;
265 if (!MO.isReg()) continue;
302 if (!MO.isReg()) continue;
375 if (!CheckOper.isReg() || !CheckOper.isDef() ||
623 if (!MO.isReg()) continue;
H A DExecutionDepsFix.cpp510 if (!MO.isReg())
583 if (!mo.isReg()) continue;
592 if (!mo.isReg()) continue;
612 if (!mo.isReg()) continue;
704 if (!mo.isReg()) continue;
H A DTwoAddressInstructionPass.cpp196 if (!MO.isReg())
269 if (!MO.isReg())
437 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
801 if (!MO.isReg())
844 if (!MO.isReg())
985 if (!MO.isReg())
1024 if (!MO.isReg())
1232 if (MO.isReg() &&
1262 if (MOI->isReg())
1381 !MI->getOperand(i).isReg() ||
[all...]
H A DAggressiveAntiDepBreaker.cpp227 if (!MO.isReg() || !MO.isImplicit())
247 if (!MO.isReg()) continue;
349 if (!MO.isReg() || !MO.isDef()) continue;
359 if (!MO.isReg() || !MO.isDef()) continue;
399 if (!MO.isReg() || !MO.isDef()) continue;
452 if (!MO.isReg() || !MO.isUse()) continue;
487 if (!MO.isReg()) continue;
H A DLiveRangeEdit.cpp91 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
254 if (!MOI->isReg())
307 if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
H A DSpiller.cpp110 if (!op.isReg() || op.getReg() != li->reg)
H A DStackMaps.cpp40 HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
46 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
63 !(MI->getOperand(ScratchIdx).isReg() &&
117 if (MOI->isReg()) {
/external/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp110 if (!MO.isReg() || !MO.isUse() ||
152 if (MO.isReg() && MO.getReg() == Reg) {
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp80 assert(dest.isReg() && "dest of a movrr is not a reg");
81 assert(src.isReg() && "src of a movrr is not a reg");
/external/llvm/lib/Target/R600/
H A DR600EmitClauseMarkers.cpp67 if (MO.isReg() && MO.getReg() == AMDGPU::ALU_LITERAL_X)
188 if (!MOI->isReg() || !MOI->isDef() ||
/external/llvm/utils/TableGen/
H A DCodeGenInstruction.h321 bool isReg() const { return Kind == K_Reg; } function in struct:llvm::CodeGenInstAlias::ResultOperand
326 Record *getRegister() const { assert(isReg()); return R; }
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp143 if (MO.isReg()) {
235 if (MO.isReg()) {
H A DR600MCCodeEmitter.cpp245 if (MO.isReg()) {
264 if (MO.isReg()) {
273 (MO.isReg() &&
301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
623 if (MO.isReg()) {
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DR600MCCodeEmitter.cpp245 if (MO.isReg()) {
264 if (MO.isReg()) {
273 (MO.isReg() &&
301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
623 if (MO.isReg()) {
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp260 if (!MO.isReg() || MO.isUndef() || MO.isUse())
269 if (!MO.isReg() || MO.isUndef() || MO.isDef())
342 if (!MO.isReg() || MO.isImplicit())
767 if (MO.isReg()) {
838 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
860 if (!MO.isReg() || MO.isUndef() || MO.isUse())
875 if (!MO.isReg() || MO.isUndef() || MO.isDef())
/external/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp111 MI->getOperand(0).isReg() &&
143 if (MO.isReg()) {
382 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ?
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUInstrInfo.cpp247 if (MO.isReg() && MO.isDef()) {
/external/llvm/include/llvm/CodeGen/
H A DMachineInstr.h698 && getOperand(0).isReg()
944 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
957 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1112 if (MO.isReg() && MO.isTied()) {
/external/llvm/lib/Target/Hexagon/
H A DHexagonFixupHwLoops.cpp169 if (MII->getOperand(1).isReg()) {
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp503 if (MO.isReg()) {
525 assert(MI.getOperand(OpNo).isReg());
569 assert(MI.getOperand(OpNo).isReg());
581 assert(MI.getOperand(OpNo).isReg());

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