| /external/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 931 enum BinaryOp { ADD, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
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| /external/llvm/lib/Analysis/ |
| H A D | DependenceAnalysis.cpp | 609 if (Direction & DVEntry::EQ)
1070 Result.DV[Level].Direction &= Dependence::DVEntry::EQ;
1077 Result.DV[Level].Direction &= Dependence::DVEntry::EQ;
1107 NewDirection |= Dependence::DVEntry::EQ;
1263 Result.DV[Level].Direction &= unsigned(~Dependence::DVEntry::EQ);
1491 DEBUG(dbgs() << "\t exploring EQ direction\n");
1510 NewDirection |= Dependence::DVEntry::EQ;
2388 Result.DV[Level - 1].Direction &= unsigned(~Dependence::DVEntry::EQ);
2532 case Dependence::DVEntry::EQ:
2569 if (Bound[Level].Lower[Dependence::DVEntry::EQ])
[all...] |
| /external/llvm/lib/MC/ |
| H A D | MCExpr.cpp | 98 case MCBinaryExpr::EQ: OS << "=="; break;
770 case MCBinaryExpr::EQ: Result = LHS == RHS; break;
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| /external/llvm/lib/MC/MCParser/ |
| H A D | AsmParser.cpp | 1107 Kind = MCBinaryExpr::EQ;
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| /external/llvm/lib/Support/ |
| H A D | regexec.c | 65 #define EQ(a, b) ((a) == (b)) macro
91 #undef EQ macro
112 #define EQ(a, b) (memcmp(a, b, m->g->nstates) == 0) macro
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| /external/llvm/lib/TableGen/ |
| H A D | Record.cpp | 934 case EQ: {
995 case EQ: Result = "!eq"; break;
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| H A D | TGParser.cpp | 927 case tgtok::XEq: Code = BinOpInit::EQ; Type = BitRecTy::get(); break;
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ConditionalCompares.cpp | 288 CC = AArch64CC::EQ;
671 .addImm(isNZ ? AArch64CC::NE : AArch64CC::EQ)
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| H A D | AArch64FastISel.cpp | 723 return AArch64CC::EQ;
814 CC = AArch64CC::EQ;
853 CC = AArch64CC::EQ;
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| H A D | AArch64ISelLowering.cpp | 858 return AArch64CC::EQ;
888 CondCode = AArch64CC::EQ;
915 CondCode = AArch64CC::EQ;
5849 case AArch64CC::EQ:
5888 case AArch64CC::EQ:
7593 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7625 if (CC == AArch64CC::EQ)
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| H A D | AArch64InstrInfo.cpp | 433 CC = AArch64CC::EQ;
437 CC = AArch64CC::EQ;
472 CC = AArch64CC::EQ;
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 2226 .Case("eq", AArch64CC::EQ)
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| /external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 193 EQ = 0x0, // Equal Equal enumerator in enum:llvm::AArch64CC::CondCode
216 case EQ: return "eq";
250 case EQ: return Z; // Z == 1
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
2206 case ARMCC::EQ: return ARMCC::EQ;
2413 CC = ARMCC::EQ;
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| H A D | ARMConstantIslandPass.cpp | 1798 if (Pred == ARMCC::EQ)
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| H A D | ARMFastISel.cpp | 1210 return ARMCC::EQ;
1297 CCMode = ARMCC::EQ;
1336 CCMode = ARMCC::EQ;
1693 .addImm(ARMCC::EQ)
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| H A D | ARMISelLowering.cpp | 1143 case ISD::SETEQ: return ARMCC::EQ;
1162 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1172 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
3187 case ARMCC::EQ:
3414 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3417 CondCode = ARMCC::EQ;
3435 // constrained to use only GE, GT, VS and EQ.
3484 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3591 // the CMP operands, and the condition code is EQ or NE, we can optimize it
7361 .addImm(ARMCC::EQ)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3140 .Case("eq", ARMCC::EQ)
4997 .Case("eq", ARMCC::EQ)
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMBaseInfo.h | 30 EQ, // Equal Equal enumerator in enum:llvm::ARMCC::CondCodes
50 case EQ: return NE;
51 case NE: return EQ;
70 case ARMCC::EQ: return "eq";
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 95 EQ = 0x01, enumerator in enum:__anon26012::HexagonHardwareLoops::Comparison::Kind
101 LEs = L | EQ,
103 GEs = G | EQ,
105 LEu = L | EQ | U,
107 GEu = G | EQ | U
542 Cmp = !Negated ? Comparison::EQ : Comparison::NE;
581 Cmp = !Negated ? Comparison::EQ : Comparison::NE;
618 // Cannot handle comparison EQ, i.e. while (A == B).
619 if (Cmp == Comparison::EQ)
640 bool CmpHasEqual = Cmp & Comparison::EQ;
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| H A D | NVPTXInstPrinter.cpp | 159 case NVPTX::PTXCmpMode::EQ:
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTX.h | 35 EQ, enumerator in enum:llvm::NVPTXCC::CondCodes
48 case NVPTXCC::EQ:
158 EQ = 0, enumerator in enum:llvm::NVPTX::PTXCmpMode::CmpMode
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1032 CONV(EQ);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 12025 // 0 - EQ
12229 // GT and EQ comparisons for integer, swapping operands and multiple
12332 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12337 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
19781 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19785 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
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| /external/llvm/test/MC/AArch64/ |
| H A D | arm64-arithmetic-encoding.s | 569 CSEL W16, W7, W27, EQ
|