/external/llvm/lib/CodeGen/ |
H A D | MachineInstr.cpp | 802 MachineBasicBlock::const_instr_iterator I2 = *Other; local 805 ++I2; 806 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
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H A D | PrologEpilogInserter.cpp | 369 MachineBasicBlock::iterator I2 = I; local 370 while (I2 != MBB->begin() && (--I2)->isTerminator()) 371 I = I2;
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/external/llvm/lib/IR/ |
H A D | Instruction.cpp | 267 static bool haveSameSpecialState(const Instruction *I1, const Instruction *I2, argument 269 assert(I1->getOpcode() == I2->getOpcode() && 273 return LI->isVolatile() == cast<LoadInst>(I2)->isVolatile() && 274 (LI->getAlignment() == cast<LoadInst>(I2)->getAlignment() || 276 LI->getOrdering() == cast<LoadInst>(I2)->getOrdering() && 277 LI->getSynchScope() == cast<LoadInst>(I2)->getSynchScope(); 279 return SI->isVolatile() == cast<StoreInst>(I2)->isVolatile() && 280 (SI->getAlignment() == cast<StoreInst>(I2)->getAlignment() || 282 SI->getOrdering() == cast<StoreInst>(I2)->getOrdering() && 283 SI->getSynchScope() == cast<StoreInst>(I2) [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 2170 // change them to I1 and I2 values via as documented: 2172 // I2 = NOT(J2 EOR S); 2174 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2179 unsigned I2 = !(J2 ^ S); local 2182 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 3801 // the encoded instruction. So here change to I1 and I2 values via: 3803 // I2 = NOT(J2 EOR S); 3805 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3810 unsigned I2 = !(J2 ^ S); local 3811 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 2 3947 unsigned I2 = !(J2 ^ S); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 86 void combine(MachineInstr *I1, MachineInstr *I2, 89 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2, 231 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such 234 MachineInstr *I2, 239 bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal(); 240 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg(); 242 // It is not safe to move I1 and I2 into one combine if I2 has a true 249 // First try to move I2 toward 233 isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2, unsigned I1DestReg, unsigned I2DestReg, bool &DoInsertAtI1) argument 450 MachineInstr *I2 = findPairable(I1, DoInsertAtI1); local 467 MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1)); local 512 combine(MachineInstr *I1, MachineInstr *I2, MachineBasicBlock::iterator &MI, bool DoInsertAtI1) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 255 MachineBasicBlock::iterator I2 = IP; local 256 while (I2 != BB->begin() && (--I2)->isTerminator()) 257 IP = I2;
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/external/llvm/lib/Transforms/Utils/ |
H A D | SimplifyCFG.cpp | 983 Instruction *I1, Instruction *I2) { 990 if (BB1V != BB2V && (BB1V==I1 || BB2V==I2)) { 1013 Instruction *I1 = BB1_Itr++, *I2 = BB2_Itr++; local 1016 DbgInfoIntrinsic *DBI2 = dyn_cast<DbgInfoIntrinsic>(I2); 1020 while (isa<DbgInfoIntrinsic>(I2)) 1021 I2 = BB2_Itr++; 1023 if (isa<PHINode>(I1) || !I1->isIdenticalToWhenDefined(I2) || 1024 (isa<InvokeInst>(I1) && !isSafeToHoistInvoke(BB1, BB2, I1, I2))) 1040 if (!I2->use_empty()) 1041 I2 982 isSafeToHoistInvoke(BasicBlock *BB1, BasicBlock *BB2, Instruction *I1, Instruction *I2) argument [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | BBVectorize.cpp | 2468 Value *I1, *I2 = nullptr; local 2473 I2 = LSV->getOperand(1); 2474 if (I2 == I1 || isa<UndefValue>(I2)) 2475 I2 = nullptr; 2480 if (!I2 && I3 != I1) 2481 I2 = I3; 2482 else if (I3 != I1 && I3 != I2) 2486 if (!I2 && I3 != I1) 2487 I2 [all...] |
/external/llvm/unittests/ADT/ |
H A D | APIntTest.cpp | 643 uint64_t I2 = 0x1000011; local 644 APInt A2(64, I2);
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H A D | IntervalMapTest.cpp | 48 UUMap::iterator I2; local 49 I2 = map.end(); 50 EXPECT_TRUE(I2 == CI);
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/external/ppp/pppd/ |
H A D | md4.c | 47 #define I2 0x98badcfe macro 110 MDp->buffer[2] = I2;
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/external/qemu/disas/ |
H A D | arm.c | 3637 unsigned int I2 = (given & 0x00000800u) >> 11; local 3642 offset |= !(I2 ^ S) << 22;
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H A D | mips.c | 1122 #define I2 INSN_ISA2 1280 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1284 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 }, 1289 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 }, 1292 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 }, 1293 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 }, 1296 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 }, 1297 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 }, 1300 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 }, 1301 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T 1121 #define I2 macro [all...] |
/external/svox/pico/lib/ |
H A D | picopam.c | 240 picoos_uint8 i2_secondary_phrase_word; /*I2 */ 323 #define I2 54 macro 1862 outVect[T_I2] = inVect[I2]; 4084 case I2: /*processor for I2*/ 4088 pam->sSyllFeats[pam->nCurrSyllable].phoneV[I2] 4101 pam->sSyllFeats[pam->nCurrSyllable].phoneV[I2] 4108 = pam->sSyllFeats[pam->nCurrSyllable].phoneV[I2]; 4113 = pam->sSyllFeats[pam->nCurrSyllable - 1].phoneV[I2]; 4757 pam->sSyllFeats[pam->nCurrSyllable].phoneV[I2] [all...] |
/external/valgrind/main/none/tests/ppc32/ |
H A D | testVMX.c | 396 signed int Iaux;//, I1, I2; 1697 signed int Iaux;//, I1, I2; 2249 signed int Iaux, I1, I2; local 3022 I2 = Saux1.e[2*i+1]*Saux2.e[2*i+1]; 3023 Iaux = I1 + I2; 3024 if ((I1>0)&&(I2>0)&&(Iaux<0)) 3026 else if ((I1<0)&&(I2<0)&&(Iaux>0)) 3029 I2 = Iaux; 3030 Iaux = I1 + I2; 3031 if ((I1>0)&&(I2> [all...] |