/external/llvm/test/MC/Mips/ |
H A D | mips64-register-names-n32-n64.s | 39 daddiu $t9, $zero, 0 # CHECK: encoding: [0x64,0x19,0x00,0x00]
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H A D | mips64-register-names-o32.s | 34 daddiu $t9, $zero, 0 # CHECK: encoding: [0x64,0x19,0x00,0x00]
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/external/openssl/crypto/aes/asm/ |
H A D | aes-mips.pl | 46 # ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25)); 105 my ($t0,$t1,$t2,$t3,$t4,$t5,$t6,$t7,$t8,$t9,$t10,$t11) = map("\$$_",(12..23)); 185 lwl $t9,1($i1) # Te3[s0] 189 lwr $t9,0($i1) # Te3[s0] 220 xor $t1,$t9 286 lbu $t9,2($i1) # Te4[s1>>24] 324 _ins $t9,24 334 xor $t1,$t9 516 lwl $t9,1($i1) # Td3[s2] 520 lwr $t9, [all...] |
/external/chromium_org/v8/src/mips/ |
H A D | code-stubs-mips.cc | 796 __ mov(t9, ra); 799 __ Jump(t9); 804 __ mov(t9, ra); 807 __ Jump(t9); 1154 // instruction past the real call into C code (the jalr(t9)), and push it. 1163 masm->mov(t9, s2); // Function pointer to t9 to conform to ABI for PIC. 1164 masm->jalr(t9); 1369 __ lw(t9, MemOperand(t0)); // Deref address. 1372 __ addiu(t9, t [all...] |
H A D | simulator-mips.h | 125 t8, t9, enumerator in enum:v8::internal::Simulator::Register
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H A D | codegen-mips.cc | 165 __ Subu(t9, t0, pref_limit); // t9 is the "last safe pref" address. 182 __ sltu(v1, t9, a0); // If a0 > t9, don't use next prefetch. 327 __ Subu(t9, t0, pref_limit); 348 __ sltu(v1, t9, a0); 383 __ sltu(v1, t9, a0); 1234 // Load the stub address to t9 and call it, 1237 t9, 1241 patcher.masm()->jalr(t9, a [all...] |
H A D | regexp-macro-assembler-mips.cc | 1076 __ li(t9, Operand(stack_guard_check)); 1078 stub.GenerateCall(masm_, t9);
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/external/chromium_org/v8/src/mips64/ |
H A D | code-stubs-mips64.cc | 791 __ mov(t9, ra); 794 __ Jump(t9); 799 __ mov(t9, ra); 802 __ Jump(t9); 1149 // instruction past the real call into C code (the jalr(t9)), and push it. 1158 masm->mov(t9, s2); // Function pointer to t9 to conform to ABI for PIC. 1159 masm->jalr(t9); 1369 __ ld(t9, MemOperand(a4)); // Deref address. 1371 __ daddiu(t9, t [all...] |
H A D | codegen-mips64.cc | 166 __ Subu(t9, a4, pref_limit); // t9 is the "last safe pref" address. 183 __ sltu(v1, t9, a0); // If a0 > t9, don't use next prefetch. 319 __ Subu(t9, a4, pref_limit); 339 __ sltu(v1, t9, a0); 1124 // Load the stub address to t9 and call it, 1127 t9, 1131 patcher.masm()->jalr(t9, a0);
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H A D | simulator-mips64.h | 154 t8, t9, enumerator in enum:v8::internal::Simulator::Register
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H A D | regexp-macro-assembler-mips64.cc | 1122 __ li(t9, Operand(stack_guard_check)); 1124 stub.GenerateCall(masm_, t9);
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/external/chromium_org/testing/gtest/test/ |
H A D | gtest-printers_test.cc | 1015 ::std::tr1::tuple<bool, int, int, int, bool, int, int, bool, int> t9( 1017 EXPECT_EQ("(false, 2, 3, 4, true, 6, 7, true, 9)", Print(t9)); 1074 ::std::tuple<bool, int, int, int, bool, int, int, bool, int> t9( 1076 EXPECT_EQ("(false, 2, 3, 4, true, 6, 7, true, 9)", Print(t9));
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/external/chromium_org/webkit/common/gpu/ |
H A D | webgraphicscontext3d_impl.cc | 139 #define DELEGATE_TO_GL_9(name, glname, t1, t2, t3, t4, t5, t6, t7, t8, t9) \ 141 t6 a6, t7 a7, t8 a8, t9 a9) { \ 146 t9, rt) \ 148 t6 a6, t7 a7, t8 a8, t9 a9) { \
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/external/clang/test/CodeGen/ |
H A D | ms-inline-asm.c | 78 void t9() { 84 // CHECK: t9
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/external/linux-tools-perf/perf-3.12.0/arch/ia64/lib/ |
H A D | memcpy_mck.S | 51 #define t9 t5 // alias! define 240 EX(.ex_handler, (p[D]) ld8 t9 = [src0], 3*8) 247 EX(.ex_handler, (p[D]) st8 [dst0] = t9, 3*8)
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/external/llvm/test/MC/Mips/mips2/ |
H A D | invalid-mips32r2.s | 62 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/valgrind/main/none/tests/mips32/ |
H A D | MoveIns.c | 307 TESTINSNMOVE("mfc1 $t9, $f24", 28, f24, t9); 336 TESTINSNMOVEt("mtc1 $t9, $f24", 30, f24, t9);
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H A D | MoveIns.stdout.exp | 26 mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a 54 mtc1 $t9, $f24 :: fs nan, rt 0xffff262d
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H A D | mips32_dsp.c | 1267 TESTDSPINST_BPOSGE32("bposge32", 14, 4, v0, t9);
1268 TESTDSPINST_BPOSGE32("bposge32", 15, 6, t9, t8);
2695 TESTDSPINST_EXTV("extpdpv $t8, $ac3, $t9", "ac3", t8, 0xffffffff, 0xffffffff,
2696 t9, 0xffff2435, 22);
2709 TESTDSPINST_EXTV("extpdpv $t1, $ac2, $t9", "ac2", t1, 0x00000018, 0x8f8f8f8f,
2710 t9, 0xeeeeeeee, 28);
2729 TESTDSPINST_EXTV("extpv $t8, $ac3, $t9", "ac3", t8, 0xffffffff, 0xffffffff,
2730 t9, 0xffff2435, 22);
2743 TESTDSPINST_EXTV("extpv $t1, $ac2, $t9", "ac2", t1, 0x00000018, 0x8f8f8f8f,
2744 t9, [all...] |
/external/gtest/test/ |
H A D | gtest-printers_test.cc | 1020 tuple<bool, int, int, int, bool, int, int, bool, int> t9( 1022 EXPECT_EQ("(false, 2, 3, 4, true, 6, 7, true, 9)", Print(t9));
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/external/pixman/demos/ |
H A D | quad2quad.c | 23 t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, local 122 t9 = px3 * py2 * x2 * x3; 125 t11 = (t10 + t9) * y2; 1084 t695 = (t542 + t43 + t9) * y2; 1263 t825 = (t431 + t9) * y2; 1542 t1023 = (t389 + t1022 + t9) * y2;
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/external/pixman/pixman/ |
H A D | pixman-mips-dspr2-asm.h | 60 #define t9 $25 macro
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 3980 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3982 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4083 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4085 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4178 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4180 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4353 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4355 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4463 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4465 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, [all...] |
/external/libcxxabi/test/ |
H A D | dynamic_cast3.cpp | 453 namespace t9 namespace 507 } // t9 2426 t9::test();
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H A D | dynamic_cast5.cpp | 1158 namespace t9 namespace 1299 } // t9 1318 t9::test();
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