/external/skia/experimental/Intersection/ |
H A D | ShapeOps.cpp | 10 namespace Op { namespace 213 } // end of Op namespace 218 Op::gDebugSortCount = Op::gDebugSortCountDefault; 223 SkTArray<Op::Contour> contours; 225 Op::EdgeBuilder builder(one, contours); 230 SkTDArray<Op::Contour*> contourList; 233 Op::Contour** currentPtr = contourList.begin(); 237 Op::Contour** listEnd = contourList.end(); 240 Op [all...] |
/external/skia/include/core/ |
H A D | SkRegion.h | 240 enum Op { enum in class:SkRegion 255 * Set this region to the result of applying the Op to this region and the 259 bool op(const SkIRect& rect, Op op) { return this->op(*this, rect, op); } 262 * Set this region to the result of applying the Op to this region and the 266 bool op(int left, int top, int right, int bottom, Op op) { 273 * Set this region to the result of applying the Op to this region and the 277 bool op(const SkRegion& rgn, Op op) { return this->op(*this, rgn, op); } 280 * Set this region to the result of applying the Op to the specified 284 bool op(const SkIRect& rect, const SkRegion& rgn, Op); 287 * Set this region to the result of applying the Op t [all...] |
/external/skia/src/pathops/ |
H A D | SkPathOpsOp.cpp | 248 bool Op(const SkPath& one, const SkPath& two, SkPathOp op, SkPath* result) { function
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 272 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 273 // be zero. Op is expected to be a target specific node. Used by DAG 278 const SDValue Op, 287 switch (Op.getOpcode()) { 291 Op.getOperand(1), 297 Op.getOperand(0), 317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const argument 319 EVT OVT = Op.getValueType(); 322 DST = LowerSDIV64(Op, DAG); 324 DST = LowerSDIV32(Op, DA 277 computeMaskedBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 335 LowerSREM(SDValue Op, SelectionDAG &DAG) const argument 354 LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const argument 420 LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const argument 474 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const argument 489 LowerSDIV24(SDValue Op, SelectionDAG &DAG) const argument 570 LowerSDIV32(SDValue Op, SelectionDAG &DAG) const argument 637 LowerSDIV64(SDValue Op, SelectionDAG &DAG) const argument 643 LowerSREM8(SDValue Op, SelectionDAG &DAG) const argument 661 LowerSREM16(SDValue Op, SelectionDAG &DAG) const argument 679 LowerSREM32(SDValue Op, SelectionDAG &DAG) const argument 742 LowerSREM64(SDValue Op, SelectionDAG &DAG) const argument [all...] |
H A D | R600KernelParameters.cpp | 258 Value *Op = GEP->getPointerOperand(); local 260 if (dyn_cast<PointerType>(Op->getType())->getAddressSpace() != Addrspace) { 261 Op = new BitCastInst(Op, PointerType::get(dyn_cast<PointerType>( 262 Op->getType())->getElementType(), Addrspace), 268 GetElementPtrInst* GEP2 = GetElementPtrInst::Create(Op, Params, Name,
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/external/clang/lib/AST/ |
H A D | DeclarationName.cpp | 346 for (unsigned Op = 0; Op < NUM_OVERLOADED_OPERATORS; ++Op) { 347 CXXOperatorNames[Op].ExtraKindOrNumArgs 348 = Op + DeclarationNameExtra::CXXConversionFunction; 349 CXXOperatorNames[Op].FETokenInfo = nullptr; 424 DeclarationNameTable::getCXXOperatorName(OverloadedOperatorKind Op) { argument 425 return DeclarationName(&CXXOperatorNames[(unsigned)Op]);
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/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | IdenticalExprChecker.cpp | 165 BinaryOperator::Opcode Op = B->getOpcode(); local 167 if (BinaryOperator::isBitwiseOp(Op)) 170 if (BinaryOperator::isLogicalOp(Op)) 173 if (BinaryOperator::isComparisonOp(Op)) 183 BinaryOperator::Opcode Op = B->getOpcode(); local 216 if ((Op == BO_EQ) || (Op == BO_NE)) { 223 if ((Op == BO_EQ) || (Op == BO_NE)) { 240 if (((Op [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | SValBuilder.cpp | 305 BinaryOperator::Opcode Op, 319 return makeNonLoc(symLHS, Op, symRHS, ResultTy); 323 return makeNonLoc(symLHS, Op, rInt->getValue(), ResultTy); 327 return makeNonLoc(lInt->getValue(), Op, symRHS, ResultTy); 304 makeSymExprValNN(ProgramStateRef State, BinaryOperator::Opcode Op, NonLoc LHS, NonLoc RHS, QualType ResultTy) argument
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H A D | SymbolManager.cpp | 238 SymbolManager::getCastSymbol(const SymExpr *Op, argument 241 SymbolCast::Profile(ID, Op, From, To); 246 new (data) SymbolCast(Op, From, To);
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/external/llvm/include/llvm/Bitcode/ |
H A D | BitstreamWriter.h | 278 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) { argument 279 assert(Op.isLiteral() && "Not a literal"); 282 assert(V == Op.getLiteralValue() && 289 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) { argument 290 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!"); 293 switch (Op.getEncoding()) { 296 if (Op.getEncodingData()) 297 Emit((unsigned)V, (unsigned)Op.getEncodingData()); 300 if (Op.getEncodingData()) 301 EmitVBR64(V, (unsigned)Op 327 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local 477 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local [all...] |
/external/llvm/include/llvm/IR/ |
H A D | NoFolder.h | 214 Instruction *CreateCast(Instruction::CastOps Op, Constant *C, argument 216 return CastInst::Create(Op, C, DestTy);
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/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 112 MCOperand Op; local 113 Op.Kind = kRegister; 114 Op.RegVal = Reg; 115 return Op; 118 MCOperand Op; local 119 Op.Kind = kImmediate; 120 Op.ImmVal = Val; 121 return Op; 124 MCOperand Op; local 125 Op 130 MCOperand Op; local 136 MCOperand Op; local 157 setOpcode(unsigned Op) argument 167 addOperand(const MCOperand &Op) argument 177 insert(iterator I, const MCOperand &Op) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 234 Value *Op = I->getOperand(0); local 237 if (isNoopBitcast(Op->getType(), I->getType(), TLI)) 238 NoopInput = Op; 242 NoopInput = Op; 249 cast<IntegerType>(Op->getType())->getBitWidth()) 250 NoopInput = Op; 258 NoopInput = Op; 260 TLI.allowTruncateForTailCall(Op->getType(), I->getType())) { 262 NoopInput = Op; 298 NoopInput = Op; [all...] |
H A D | TargetLoweringObjectFileImpl.cpp | 942 StringRef Op = MDOption->getString(); local 945 if (Op.find(" ") != StringRef::npos) { 951 Escaped.append(Op); 954 Escaped.append(Op);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 125 TargetLowering::AsmOperandInfo &Op = Ops[I]; local 126 if (Op.Type == InlineAsm::isClobber) { 128 TLI->ComputeConstraintToUse(Op, SDValue(), DAG); 130 TLI->getRegForInlineAsmConstraint(Op.ConstraintCode, 131 Op.ConstraintVT);
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/external/llvm/lib/LTO/ |
H A D | LTOModule.cpp | 599 StringRef Op = _linkeropt_strings. local 602 getObjFileLowering().getDepLibFromLinkerOpt(Op); 605 else if (!Op.empty()) 606 _linkeropts.push_back(Op.data());
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/external/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 199 MachineOperand *Op = MI->findRegisterDefOperand(Reg); local 201 if (!Op) 204 MachineInstr *Def = Op->getParent();
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 212 MachineOperand &Op = MI->getOperand(I); local 213 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) 215 Op.setIsKill(false); 367 MachineOperand &Op = MI->getOperand(OpdIdx); local 370 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) 374 unsigned Reg = Op 399 MachineOperand &Op = MI->getOperand(I); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 233 unsigned Op, raw_ostream &O, 235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 236 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 237 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp); 271 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier); 275 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier); 276 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm(); 285 unsigned Op, raw_ostream &O, 287 assert(isMem(MI, Op) && "Invalid memory reference!"); 288 const MachineOperand &Segment = MI->getOperand(Op 232 printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr) argument 284 printMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr) argument 296 printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr, unsigned AsmVariant = 1) argument [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineLoadStoreAlloca.cpp | 361 Value *Op = LI.getOperand(0); local 366 getOrEnforceKnownAlignment(Op, DL->getPrefTypeAlignment(LI.getType()),DL); 378 if (isa<CastInst>(Op)) 390 if (Value *AvailableVal = FindAvailableLoadedValue(Op, LI.getParent(), BBI,6)) 394 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(Op)) { 403 Constant::getNullValue(Op->getType()), &LI); 410 if (isa<UndefValue>(Op) || 411 (isa<ConstantPointerNull>(Op) && LI.getPointerAddressSpace() == 0)) { 416 Constant::getNullValue(Op->getType()), &LI); 421 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Op)) [all...] |
H A D | InstCombineSelect.cpp | 312 /// SimplifyWithOpReplaced - See if V simplifies when its operand Op is 314 static Value *SimplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp, argument 318 if (V == Op) 327 if (B->getOperand(0) == Op) 329 if (B->getOperand(1) == Op) 335 if (C->getOperand(0) == Op) 338 if (C->getOperand(1) == Op) 345 // If all operands are constant after substituting Op for RepOp then we can 351 if (I->getOperand(i) == Op)
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/external/llvm/lib/Transforms/Scalar/ |
H A D | DeadStoreElimination.cpp | 134 Value *Op = DeadInst->getOperand(op); local 138 if (!Op->use_empty()) continue; 140 if (Instruction *OpI = dyn_cast<Instruction>(Op))
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/external/llvm/lib/Transforms/Utils/ |
H A D | BuildLibCalls.cpp | 290 /// Append a suffix to the function name according to the type of 'Op'. 291 static void AppendTypeSuffix(Value *Op, StringRef &Name, SmallString<20> &NameBuffer) { argument 292 if (!Op->getType()->isDoubleTy()) { 295 if (Op->getType()->isFloatTy()) 306 /// 'floor'). This function is known to take a single of type matching 'Op' and 307 /// returns one value with the same type. If 'Op' is a long double, 'l' is 308 /// added as the suffix of name, if 'Op' is a float, we add a 'f' suffix. 309 Value *llvm::EmitUnaryFloatFnCall(Value *Op, StringRef Name, IRBuilder<> &B, argument 312 AppendTypeSuffix(Op, Name, NameBuffer); 315 Value *Callee = M->getOrInsertFunction(Name, Op [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.cpp | 154 CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) { argument 155 if (Op.empty() || Op[0] != '$') 156 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'"); 158 std::string OpName = Op.substr(1); 166 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'"); 177 " whole operand part of complex operand '" + Op + "'"); 186 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'"); 194 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'"); 209 std::pair<unsigned,unsigned> Op local 278 std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false); local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 272 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 273 // be zero. Op is expected to be a target specific node. Used by DAG 278 const SDValue Op, 287 switch (Op.getOpcode()) { 291 Op.getOperand(1), 297 Op.getOperand(0), 317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const argument 319 EVT OVT = Op.getValueType(); 322 DST = LowerSDIV64(Op, DAG); 324 DST = LowerSDIV32(Op, DA 277 computeMaskedBitsForTargetNode( const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument 335 LowerSREM(SDValue Op, SelectionDAG &DAG) const argument 354 LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const argument 420 LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const argument 474 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const argument 489 LowerSDIV24(SDValue Op, SelectionDAG &DAG) const argument 570 LowerSDIV32(SDValue Op, SelectionDAG &DAG) const argument 637 LowerSDIV64(SDValue Op, SelectionDAG &DAG) const argument 643 LowerSREM8(SDValue Op, SelectionDAG &DAG) const argument 661 LowerSREM16(SDValue Op, SelectionDAG &DAG) const argument 679 LowerSREM32(SDValue Op, SelectionDAG &DAG) const argument 742 LowerSREM64(SDValue Op, SelectionDAG &DAG) const argument [all...] |