Searched refs:MCID (Results 1 - 25 of 55) sorted by relevance

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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInst.h24 // MCID is set during instruction lowering.
27 const MCInstrDesc *MCID; member in class:llvm::HexagonMCInst
34 MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {};
36 MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; };
51 const MCInstrDesc& getDesc(void) const { return *MCID; };
H A DHexagonMCInst.cpp33 const uint64_t F = MCID->TSFlags;
40 return (!MCID->isPseudo() &&
52 const uint64_t F = MCID->TSFlags;
58 const uint64_t F = MCID->TSFlags;
64 const uint64_t F = MCID->TSFlags;
70 const uint64_t F = MCID->TSFlags;
118 const uint64_t F = MCID->TSFlags;
124 const uint64_t F = MCID->TSFlags;
130 const uint64_t F = MCID->TSFlags;
136 const uint64_t F = MCID
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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h99 namespace MCID { namespace in namespace:llvm
210 return Flags & (1 << MCID::Variadic);
216 return Flags & (1 << MCID::HasOptionalDef);
223 return Flags & (1 << MCID::Pseudo);
228 return Flags & (1 << MCID::Return);
233 return Flags & (1 << MCID::Call);
240 return Flags & (1 << MCID::Barrier);
250 return Flags & (1 << MCID::Terminator);
258 return Flags & (1 << MCID::Branch);
264 return Flags & (1 << MCID
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/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h31 const MCInstrDesc &MCID = MI->getDesc(); local
33 if (MCID.mayLoad())
35 if (MCID.mayStore())
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
32 if (!MCID)
35 if (!MCID->mayLoad())
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
58 if (!MCID)
61 if (!MCID->isBranch())
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, argument
92 unsigned IIC = MCID->getSchedClass();
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
149 const MCInstrDesc *MCID local
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode); local
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H A DPPCHazardRecognizers.h33 bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots);
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc(); local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
H A DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
453 const MCInstrDesc &MCID = MI.getDesc(); local
455 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
766 const MCInstrDesc &MCID = MI.getDesc(); local
775 Binary |= getAddrModeSBit(MI, MCID);
920 const MCInstrDesc &MCID,
990 const MCInstrDesc &MCID) const {
991 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
1002 const MCInstrDesc &MCID local
919 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1100 const MCInstrDesc &MCID = MI.getDesc(); local
1178 const MCInstrDesc &MCID = MI.getDesc(); local
1263 const MCInstrDesc &MCID = MI.getDesc(); local
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H A DThumb2SizeReduction.cpp213 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument
214 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
549 const MCInstrDesc &MCID = MI->getDesc(); local
550 if (MCID.hasOptionalDef() &&
551 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
698 const MCInstrDesc &MCID = MI->getDesc(); local
699 if (MCID.hasOptionalDef()) {
700 unsigned NumOps = MCID.getNumOperands();
726 unsigned NumOps = MCID.getNumOperands();
728 if (i < NumOps && MCID
762 const MCInstrDesc &MCID = MI->getDesc(); local
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H A DMLxExpansionPass.cpp187 const MCInstrDesc &MCID = MI->getDesc(); local
188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
191 unsigned Opcode = MCID.getOpcode();
344 const MCInstrDesc &MCID = MI->getDesc(); local
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
362 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
H A DThumb2ITBlockPass.cpp142 const MCInstrDesc &MCID = MI->getDesc(); local
144 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h230 const MCInstrDesc &MCID) {
231 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
239 const MCInstrDesc &MCID,
241 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
252 const MCInstrDesc &MCID,
255 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
263 const MCInstrDesc &MCID,
266 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
274 const MCInstrDesc &MCID,
278 return BuildMI(BB, MII, DL, MCID, DestRe
228 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID) argument
237 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
249 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
260 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
271 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
289 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
299 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
309 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID) argument
326 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID) argument
336 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
348 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *MD) argument
373 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, bool IsIndirect, unsigned Reg, unsigned Offset, const MDNode *MD) argument
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H A DMachineInstr.h71 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
266 const MCInstrDesc &getDesc() const { return *MCID; }
270 int getOpcode() const { return MCID->Opcode; }
384 return hasProperty(MCID::Variadic, Type);
390 return hasProperty(MCID::HasOptionalDef, Type);
397 return hasProperty(MCID::Pseudo, Type);
401 return hasProperty(MCID::Return, Type);
405 return hasProperty(MCID::Call, Type);
412 return hasProperty(MCID
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/external/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp129 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
130 if (!MCID) {
134 unsigned idx = MCID->getSchedClass();
185 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
186 assert(MCID && "The scheduler must filter non-machineinstrs");
187 if (DAG->TII->isZeroCost(MCID->Opcode))
194 unsigned idx = MCID->getSchedClass();
H A DMachineInstr.cpp538 if (MCID->ImplicitDefs)
539 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
541 if (MCID->ImplicitUses)
542 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
551 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0),
555 if (unsigned NumOps = MCID->getNumOperands() +
556 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
568 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
640 assert(MCID
1152 const MCInstrDesc &MCID = getDesc(); local
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H A DTargetInstrInfo.cpp42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
45 if (OpNum >= MCID.getNumOperands())
48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
123 const MCInstrDesc &MCID = MI->getDesc(); local
124 bool HasDef = MCID.getNumDefs();
186 const MCInstrDesc &MCID = MI->getDesc(); local
187 if (!MCID.isCommutable())
191 SrcOpIdx1 = MCID.getNumDefs();
221 const MCInstrDesc &MCID local
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H A DMachineVerifier.cpp774 const MCInstrDesc &MCID = MI->getDesc(); local
775 if (MI->getNumOperands() < MCID.getNumOperands()) {
777 *OS << MCID.getNumOperands() << " operands expected, but "
818 const MCInstrDesc &MCID = MI->getDesc(); local
820 // The first MCID.NumDefs operands must be explicit register defines
821 if (MONum < MCID.getNumDefs()) {
822 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
829 } else if (MONum < MCID.getNumOperands()) {
830 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
834 !(MI->isVariadic() && MONum == MCID
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/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h153 const MCInstrDesc &MCID = MI->getDesc(); local
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
/external/llvm/lib/Target/AArch64/
H A DAArch64ConditionalCompares.cpp593 const MCInstrDesc &MCID = TII->get(Opc); local
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
598 BuildMI(*Head, Head->end(), TermDL, MCID)
605 TII->getRegClass(MCID, 1, TRI, *MF));
650 const MCInstrDesc &MCID = TII->get(Opc); local
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
657 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
H A DAArch64RegisterInfo.cpp294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); local
297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
300 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
/external/chromium_org/third_party/skia/experimental/PdfViewer/pdfparser/native/pdfapi/
H A DSkPdfMarkedContentReferenceDictionary_autogen.cpp59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { function in class:SkPdfMarkedContentReferenceDictionary
60 SkPdfNativeObject* ret = get("MCID", "");
68 return get("MCID", "") != NULL;
/external/skia/experimental/PdfViewer/pdfparser/native/pdfapi/
H A DSkPdfMarkedContentReferenceDictionary_autogen.cpp59 int64_t SkPdfMarkedContentReferenceDictionary::MCID(SkPdfNativeDoc* doc) { function in class:SkPdfMarkedContentReferenceDictionary
60 SkPdfNativeObject* ret = get("MCID", "");
68 return get("MCID", "") != NULL;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp258 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
259 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
260 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
265 if (MCID.isCommutable())
436 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
437 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
438 unsigned NumRes = MCID.getNumDefs();
439 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
514 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
515 if (!MCID
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H A DInstrEmitter.cpp320 const MCInstrDesc &MCID = MIB->getDesc(); local
321 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
322 MCID.OpInfo[IIOpNum].isOptionalDef();
357 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
843 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
844 UsedRegs.append(MCID.getImplicitUses(),
845 MCID.getImplicitUses() + MCID.getNumImplicitUses());
/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp102 const MCInstrDesc &MCID = get(Opc); local
103 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);

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