Searched refs:MI (Results 1 - 25 of 514) sorted by relevance

1234567891011>>

/external/llvm/lib/Target/ARM/
H A DARMOptimizeBarriersPass.cpp40 // The current implementation allows this iif MI does not have any possible
42 static bool CanMovePastDMB(const MachineInstr *MI) { argument
43 return !(MI->mayLoad() ||
44 MI->mayStore() ||
45 MI->hasUnmodeledSideEffects() ||
46 MI->isCall() ||
47 MI->isReturn());
63 for (auto &MI : MBB) {
64 if (MI.getOpcode() == ARM::DMB) {
68 if (MI
[all...]
H A DARMCodeEmitter.cpp79 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
87 void emitInstruction(const MachineInstr &MI);
93 void emitConstPoolInstruction(const MachineInstr &MI);
94 void emitMOVi32immInstruction(const MachineInstr &MI);
95 void emitMOVi2piecesInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
97 void emitPseudoMoveInstruction(const MachineInstr &MI);
99 void emitPseudoInstruction(const MachineInstr &MI);
100 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
106 unsigned getAddrModeSBit(const MachineInstr &MI,
154 getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const argument
166 NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) const argument
168 NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) const argument
170 NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) const argument
172 NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val) const argument
176 getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) const argument
178 getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) const argument
180 getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
182 getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
184 getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
186 getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
188 getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
190 getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
192 getUnconditionalBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
194 getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
196 getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
198 getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) const argument
200 getCCOutOpValue(const MachineInstr &MI, unsigned Op) const argument
202 getSOImmOpValue(const MachineInstr &MI, unsigned Op) const argument
204 getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) const argument
206 getSORegRegOpValue(const MachineInstr &MI, unsigned Op) const argument
208 getSORegImmOpValue(const MachineInstr &MI, unsigned Op) const argument
210 getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) const argument
212 getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) const argument
214 getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) const argument
216 getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) const argument
218 getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) const argument
220 getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) const argument
222 getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) const argument
224 getT2SORegOpValue(const MachineInstr &MI, unsigned Op) const argument
226 getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) const argument
228 getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) const argument
230 getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, unsigned Op) const argument
233 getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) const argument
235 getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) const argument
237 getBitfieldInvertedMaskOpValue(const MachineInstr &MI, unsigned Op) const argument
239 getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) const argument
242 getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) const argument
263 getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const argument
267 getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) const argument
269 getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) const argument
271 getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) const argument
273 getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const argument
275 getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) const argument
277 getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) const argument
279 getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) const argument
281 getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const argument
312 getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) const argument
315 getRegisterListOpValue(const MachineInstr &MI, unsigned Op) const argument
318 getShiftRight8Imm(const MachineInstr &MI, unsigned Op) const argument
320 getShiftRight16Imm(const MachineInstr &MI, unsigned Op) const argument
322 getShiftRight32Imm(const MachineInstr &MI, unsigned Op) const argument
324 getShiftRight64Imm(const MachineInstr &MI, unsigned Op) const argument
417 getMovi32Value(const MachineInstr &MI, const MachineOperand &MO, unsigned Reloc) argument
442 getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const argument
529 emitInstruction(const MachineInstr &MI) argument
622 emitConstPoolInstruction(const MachineInstr &MI) argument
685 emitMOVi32immInstruction(const MachineInstr &MI) argument
721 emitMOVi2piecesInstruction(const MachineInstr &MI) argument
763 emitLEApcrelJTInstruction(const MachineInstr &MI) argument
790 emitPseudoMoveInstruction(const MachineInstr &MI) argument
835 emitPseudoInstruction(const MachineInstr &MI) argument
919 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
989 getAddrModeSBit(const MachineInstr &MI, const MCInstrDesc &MCID) const argument
999 emitDataProcessingInstruction(const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) argument
1097 emitLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) argument
1176 emitMiscLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRn) argument
1262 emitLoadStoreMultipleInstruction(const MachineInstr &MI) argument
[all...]
/external/llvm/lib/Target/X86/InstPrinter/
H A DX86ATTInstPrinter.h30 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
35 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
39 void printInstruction(const MCInst *MI, raw_ostream &OS);
42 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
43 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
46 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
47 void printSrcIdx(const MCInst *MI, unsigne
52 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
56 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
59 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
62 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
65 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
68 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
71 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
74 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
77 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
80 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
83 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
86 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
89 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
92 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
96 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
99 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
102 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
105 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
108 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
111 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
114 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
117 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
120 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
123 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
126 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
129 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
[all...]
H A DX86IntelInstPrinter.h31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
34 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
41 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printDstIdx(const MCInst *MI, unsigne
47 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
52 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
56 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
60 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
64 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
68 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
72 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
76 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
80 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
84 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
88 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
92 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
96 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
100 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
106 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
110 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
114 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
118 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
122 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
126 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
130 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
134 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
138 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
142 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
146 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
150 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
[all...]
H A DX86InstComments.cpp31 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, argument
37 switch (MI->getOpcode()) {
40 DestName = getRegName(MI->getOperand(0).getReg());
41 Src1Name = getRegName(MI->getOperand(1).getReg());
42 Src2Name = getRegName(MI->getOperand(2).getReg());
43 if(MI->getOperand(3).isImm())
44 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
49 Src2Name = getRegName(MI->getOperand(2).getReg());
50 Src1Name = getRegName(MI->getOperand(1).getReg());
51 DestName = getRegName(MI
[all...]
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.h29 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigne
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUCodeEmitter.h21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, argument
24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, argument
28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, argument
32 virtual uint64_t VOPPostEncode(const MachineInstr &MI, argument
36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI, argument
40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo) argument
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUCodeEmitter.h21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, argument
24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, argument
28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, argument
32 virtual uint64_t VOPPostEncode(const MachineInstr &MI, argument
36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI, argument
40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo) argument
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.h29 void printInstruction(const MCInst *MI, raw_ostream &O);
32 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
35 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 static void printIfSet(const MCInst *MI, unsigne
[all...]
/external/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp50 bool LowerSubregToReg(MachineInstr *MI);
51 bool LowerCopy(MachineInstr *MI);
53 void TransferImplicitDefs(MachineInstr *MI);
63 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
65 /// operands from MI to the replacement instruction.
67 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { argument
68 MachineBasicBlock::iterator CopyMI = MI;
71 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
72 MachineOperand &MO = MI->getOperand(i);
79 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { argument
136 LowerCopy(MachineInstr *MI) argument
194 MachineInstr *MI = mi; local
[all...]
H A DErlangGC.cpp31 MachineBasicBlock::iterator MI,
54 MachineBasicBlock::iterator MI,
58 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
65 for (MachineBasicBlock::iterator MI = BBI->begin(), ME = BBI->end();
66 MI != ME; ++MI)
68 if (MI->getDesc().isCall()) {
71 if (MI->getDesc().isTerminator())
75 MachineBasicBlock::iterator RAI = MI; ++RAI;
76 MCSymbol* Label = InsertLabel(*MI
53 InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const argument
[all...]
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.cpp7 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
9 printInstruction(MI, OS);
14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
17 const MCOperand &Op = MI->getOperand(OpNo);
29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument
31 printOperand(MI, OpNo, O);
/external/llvm/lib/Target/Mips/
H A DMipsCodeEmitter.cpp82 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
84 void emitInstruction(MachineBasicBlock::instr_iterator MI,
102 unsigned getMachineOpValue(const MachineInstr &MI,
105 unsigned getRelocation(const MachineInstr &MI,
108 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
109 unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const;
110 unsigned getBranchTargetOpValueMM(const MachineInstr &MI,
113 unsigned getBranchTarget21OpValue(const MachineInstr &MI,
115 unsigned getBranchTarget26OpValue(const MachineInstr &MI,
117 unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigne
172 getRelocation(const MachineInstr &MI, const MachineOperand &MO) const argument
187 getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const argument
201 getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const argument
207 getBranchTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const argument
213 getBranchTarget21OpValue(const MachineInstr &MI, unsigned OpNo) const argument
219 getBranchTarget26OpValue(const MachineInstr &MI, unsigned OpNo) const argument
225 getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const argument
231 getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const argument
238 getMemEncoding(const MachineInstr &MI, unsigned OpNo) const argument
246 getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const argument
252 getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const argument
258 getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const argument
264 getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const argument
271 getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const argument
277 getSimm18Lsl3Encoding(const MachineInstr &MI, unsigned OpNo) const argument
283 getSimm19Lsl2Encoding(const MachineInstr &MI, unsigned OpNo) const argument
291 getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const argument
342 emitInstruction(MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB) argument
368 expandACCInstr(MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB, unsigned Opc) const argument
376 expandPseudos(MachineBasicBlock::instr_iterator &MI, MachineBasicBlock &MBB) const argument
[all...]
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.cpp7 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument
9 printInstruction(MI, OS);
14 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
17 const MCOperand &Op = MI->getOperand(OpNo);
29 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo, argument
31 printOperand(MI, OpNo, O);
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp125 MachineInstr &MI = *II; local
126 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
129 MachineFunction &MF = *MI.getParent()->getParent();
145 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
146 !TII.isSpillPredRegOp(&MI)) {
148 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
150 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
153 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
162 if ( (MI.getOpcode() == Hexagon::LDriw) ||
163 (MI
[all...]
H A DHexagonSplitTFRCondSets.cpp92 MachineInstr *MI = MII; local
94 switch(MI->getOpcode()) {
98 int DestReg = MI->getOperand(0).getReg();
99 int SrcReg1 = MI->getOperand(2).getReg();
100 int SrcReg2 = MI->getOperand(3).getReg();
102 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
103 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
107 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
115 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Opc1),
116 DestReg).addReg(MI
[all...]
H A DHexagonMachineFunctionInfo.h48 void addAllocaAdjustInst(MachineInstr* MI) { argument
49 AllocaAdjustInsts.push_back(MI);
58 void setStartPacket(MachineInstr* MI) { argument
59 PacketInfo[MI] |= Hexagon::StartPacket;
61 void setEndPacket(MachineInstr* MI) { argument
62 PacketInfo[MI] |= Hexagon::EndPacket;
64 bool isStartPacket(const MachineInstr* MI) const {
65 return (PacketInfo.count(MI) &&
66 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
68 bool isEndPacket(const MachineInstr* MI) cons
[all...]
/external/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34 return MI.getOperand(OpNo).getReg() == R;
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
81 switch (MI->getOpcode()) {
91 printSaveRestore(MI, O);
96 printSaveRestore(MI, O);
101 printSaveRestore(MI, O);
106 printSaveRestore(MI, O);
112 if (!printAliasInstr(MI,
188 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
205 printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O) argument
214 printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O) argument
224 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
235 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) argument
245 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
251 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) argument
255 printAlias(const char *Str, const MCInst &MI, unsigned OpNo, raw_ostream &OS) argument
262 printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, unsigned OpNo1, raw_ostream &OS) argument
271 printAlias(const MCInst &MI, raw_ostream &OS) argument
317 printSaveRestore(const MCInst *MI, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/R600/
H A DSILowerControlFlow.cpp76 void SkipIfDead(MachineInstr &MI);
78 void If(MachineInstr &MI);
79 void Else(MachineInstr &MI);
80 void Break(MachineInstr &MI);
81 void IfBreak(MachineInstr &MI);
82 void ElseBreak(MachineInstr &MI);
83 void Loop(MachineInstr &MI);
84 void EndCf(MachineInstr &MI);
86 void Kill(MachineInstr &MI);
87 void Branch(MachineInstr &MI);
145 SkipIfDead(MachineInstr &MI) argument
179 If(MachineInstr &MI) argument
197 Else(MachineInstr &MI) argument
216 Break(MachineInstr &MI) argument
230 IfBreak(MachineInstr &MI) argument
245 ElseBreak(MachineInstr &MI) argument
260 Loop(MachineInstr &MI) argument
276 EndCf(MachineInstr &MI) argument
289 Branch(MachineInstr &MI) argument
296 Kill(MachineInstr &MI) argument
327 InitM0ForLDS(MachineBasicBlock::iterator MI) argument
332 LoadM0(MachineInstr &MI, MachineInstr *MovRel) argument
399 IndirectSrc(MachineInstr &MI) argument
420 IndirectDst(MachineInstr &MI) argument
460 MachineInstr &MI = *I; local
[all...]
/external/llvm/lib/Target/SystemZ/InstPrinter/
H A DSystemZInstPrinter.h30 void printInstruction(const MCInst *MI, raw_ostream &O);
42 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
46 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
47 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
48 void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
49 void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O);
50 void printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
51 void printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
52 void printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
53 void printU8ImmOperand(const MCInst *MI, in
[all...]
/external/llvm/lib/Target/Hexagon/InstPrinter/
H A DHexagonInstPrinter.h30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
31 void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
38 void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
39 void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
40 void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,
42 void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
44 void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
46 void printMEMriOperand(const MCInst *MI, unsigne
65 printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument
67 printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const argument
[all...]
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp38 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
44 uint64_t getBinaryCodeForInstr(const MCInst &MI,
49 // MO in MI. Fixups is the list of fixups against MI.
50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
58 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
61 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
64 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
67 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
70 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigne
82 getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
87 getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
103 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
117 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
128 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
138 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
148 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
159 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
171 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
182 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset) const argument
[all...]
/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.h31 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
35 virtual void printInstruction(const MCInst *MI, raw_ostream &O);
36 virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
37 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
46 bool printSysAlias(const MCInst *MI, raw_ostream &O);
48 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
49 void printHexImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
53 void printPostIncOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { argument
54 printPostIncOperand(MI, OpN
70 printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
83 printUImm12Offset(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
88 printAMIndexedWB(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.h35 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
38 void printInstruction(const MCInst *MI, raw_ostream &O);
42 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printPredicateOperand(const MCInst *MI, unsigned OpNo,
46 void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
48 void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
49 void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printU16ImmOperand(const MCInst *MI, unsigne
[all...]
/external/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.cpp46 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
49 if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
50 printInstruction(MI, O);
54 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O) argument
56 switch (MI->getOpcode()) {
60 if (MI->getNumOperands() != 3)
62 if (!MI->getOperand(0).isReg())
64 switch (MI->getOperand(0).getReg()) {
67 if (MI
107 printOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
126 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O, const char *Modifier) argument
149 printCCOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
173 printGetPCX(const MCInst *MI, unsigned opNum, raw_ostream &O) argument
[all...]

Completed in 420 milliseconds

1234567891011>>