Searched refs:Tmp1 (Results 1 - 25 of 26) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp571 SDValue Tmp1 = Vec; local
581 EVT VT = Tmp1.getValueType();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
1560 SDValue Tmp1 = Node->getOperand(0);
1611 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1626 SDValue Tmp1 = SDValue(Node, 0);
1629 SDValue Chain = Tmp1.getOperand(0);
1642 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1644 Tmp1
[all...]
H A DLegalizeFloatTypes.cpp1416 SDValue Tmp1, Tmp2, Tmp3; local
1417 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1421 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1422 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1426 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1427 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp
[all...]
H A DLegalizeVectorOps.cpp343 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); local
344 if (Tmp1.getNode()) {
345 Result = Tmp1;
H A DLegalizeIntegerTypes.cpp2609 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2611 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2617 SDValue Tmp1, Tmp2; local
2620 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2622 if (!Tmp1.getNode())
2623 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2634 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2657 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2658 NewLHS, Tmp1, Tmp2);
/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/
H A Dcmsintrp.c842 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
932 Tmp1[OutChan] = (cmsUInt16Number) c0 + ROUND_FIXED_TO_INT(_cmsToFixedDomain(Rest));
1002 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]);
1023 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1039 TetrahedralInterpFloat(Input + 1, Tmp1, &p1);
1047 cmsFloat32Number y0 = Tmp1[i];
1067 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1084 Eval4Inputs(Input + 1, Tmp1, &p1);
1093 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]);
1110 cmsFloat32Number Tmp1[MAX_STAGE_CHANNEL local
1155 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1197 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1241 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1282 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1327 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
1367 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local
[all...]
/external/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp176 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), local
180 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16");
190 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), local
199 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2");
220 Value* Tmp1 = Builder.CreateLShr(V, local
250 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4");
/external/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp132 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); local
135 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor);
136 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1);
137 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp);
256 Value *Tmp1 = Builder.CreateCall2(CTLZ, Dividend, True); local
257 Value *SR = Builder.CreateSub(Tmp0, Tmp1);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp243 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local
257 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
273 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
/external/llvm/lib/Target/R600/
H A DAMDGPUPromoteAlloca.cpp328 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ); local
329 Value *TID = Builder.CreateAdd(Tmp0, Tmp1);
H A DAMDGPUISelLowering.cpp1790 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1791 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local
1804 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1805 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1820 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1821 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1988 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); local
1989 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2004 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); local
2005 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySig
2078 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT, local
[all...]
/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/
H A Dstructs.h251 double Tmp1[MAXFFTSIZE]; member in struct:__anon17042
H A Dfft.c338 if (fftstate->Tmp0 == NULL || fftstate->Tmp1 == NULL || fftstate->Tmp2 == NULL || fftstate->Tmp3 == NULL
345 Itmp = (REAL *) fftstate->Tmp1;
/external/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp108 ExplodedNodeSet Tmp1, Tmp2; local
116 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1;
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2342 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2343 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2346 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2357 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2486 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2487 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2494 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; local
2495 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2496 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2548 SDValue Ops[] = { Tmp0, Tmp1, Tmp
[all...]
H A DX86ISelLowering.cpp11354 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, local
11378 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
14290 SDValue Tmp1 = SDValue(Node, 0); local
14293 SDValue Chain = Tmp1.getOperand(0);
14306 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14308 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14310 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14316 SDValue Ops[2] = { Tmp1, Tmp2 };
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1427 SmallVector<MachineOperand,2> Tmp1; local
1430 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1436 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false);
H A DHexagonISelLowering.cpp1098 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); local
1099 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1119 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1120 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
/external/llvm/lib/Support/
H A DAPInt.cpp797 unsigned Tmp1 = unsigned(VAL >> 16);
798 Tmp1 = ByteSwap_32(Tmp1);
801 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1);
/external/clang/lib/CodeGen/
H A DCGExprComplex.cpp773 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c local
775 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3871 SDValue Tmp1 = Op.getOperand(1); local
3874 EVT SrcVT = Tmp1.getValueType();
3892 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3894 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3895 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3898 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3899 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3902 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4083 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local
4117 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); local
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1695 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local
1699 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1755 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); local
1759 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1964 SDValue Tmp1 = ST->getChain(); local
1972 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp500 SDValue Tmp1, Tmp2; local
2952 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local
2955 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2966 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local
2969 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
H A DPPCISelLowering.cpp6389 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
6392 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6418 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
6421 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6446 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
6449 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2753 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); local
2754 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4124 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local
4133 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4168 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); local
4174 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);

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