/external/llvm/lib/CodeGen/ |
H A D | IntrinsicLowering.cpp | 178 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), local 180 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16"); 188 Value *Tmp2 = Builder.CreateLShr(V, ConstantInt::get(V->getType(), 8), local 195 Tmp2 = Builder.CreateAnd(Tmp2, 199 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2"); 200 V = Builder.CreateOr(Tmp4, Tmp2, "bswap.i32"); 217 Value* Tmp2 = Builder.CreateLShr(V, local 243 Tmp2 [all...] |
/external/pdfium/core/src/fxcodec/lcms2/lcms2-2.6/src/ |
H A D | cmsintrp.c | 842 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 996 Tmp2[OutChan] = (cmsUInt16Number) c0 + ROUND_FIXED_TO_INT(_cmsToFixedDomain(Rest)); 1002 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]); 1023 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1043 TetrahedralInterpFloat(Input + 1, Tmp2, &p1); 1048 cmsFloat32Number y1 = Tmp2[i]; 1067 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1089 Eval4Inputs(Input + 1, Tmp2, &p1); 1093 Output[i] = LinearInterp(rk, Tmp1[i], Tmp2[i]); 1110 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNEL local 1155 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1197 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1241 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1282 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1327 cmsUInt16Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local 1367 cmsFloat32Number Tmp1[MAX_STAGE_CHANNELS], Tmp2[MAX_STAGE_CHANNELS]; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 572 SDValue Tmp2 = Val; local 602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 1561 SDValue Tmp2 = Node->getOperand(1); 1566 EVT FloatVT = Tmp2.getValueType(); 1570 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1578 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1627 SDValue Tmp2 = SDValue(Node, 1); 1636 SDValue Size = Tmp2.getOperand(1); 1648 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1653 Results.push_back(Tmp2); [all...] |
H A D | SelectionDAG.cpp | 2419 unsigned Tmp, Tmp2; local 2450 Tmp2 = ComputeNumSignBits(Op.getOperand(0), Depth+1); 2451 return std::max(Tmp, Tmp2); 2476 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2477 FirstAnswer = std::min(Tmp, Tmp2); 2487 Tmp2 = ComputeNumSignBits(Op.getOperand(2), Depth+1); 2488 return std::min(Tmp, Tmp2); 2550 Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1); 2551 if (Tmp2 == 1) return 1; 2552 return std::min(Tmp, Tmp2) [all...] |
H A D | LegalizeIntegerTypes.cpp | 2610 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2611 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2617 SDValue Tmp1, Tmp2; local 2627 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), 2629 if (!Tmp2.getNode()) 2630 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2635 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2646 NewLHS = Tmp2; 2658 NewLHS, Tmp1, Tmp2);
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H A D | LegalizeFloatTypes.cpp | 1416 SDValue Tmp1, Tmp2, Tmp3; local 1419 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), 1421 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 1424 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()), 1426 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
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/external/llvm/lib/Transforms/Utils/ |
H A D | IntegerDivision.cpp | 133 Value *Tmp2 = Builder.CreateXor(Tmp, Dividend); local 134 Value *U_Dvnd = Builder.CreateSub(Tmp2, Tmp); 273 Value *Tmp2 = Builder.CreateSub(MSB, SR); local 274 Value *Q = Builder.CreateShl(Dividend, Tmp2);
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineC.cpp | 31 ExplodedNodeSet Tmp2; local 56 evalStore(Tmp2, B, LHS, *it, state->BindExpr(B, LCtx, ExprVal), 62 StmtNodeBuilder Bldr(*it, Tmp2, *currBldrCtx); 179 evalStore(Tmp2, B, LHS, *I, state, location, LHSVal); 184 getCheckerManager().runCheckersForPostStmt(Dst, Tmp2, B, *this);
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H A D | CheckerManager.cpp | 108 ExplodedNodeSet Tmp1, Tmp2; local 116 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1;
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/external/llvm/lib/Analysis/ |
H A D | ValueTracking.cpp | 1880 unsigned Tmp, Tmp2; local 1964 Tmp2 = ShAmt->getZExtValue(); 1965 if (Tmp2 >= TyBits || // Bad shift. 1966 Tmp2 >= Tmp) break; // Shifted all sign bits out. 1967 return Tmp - Tmp2; 1977 Tmp2 = ComputeNumSignBits(U->getOperand(1), DL, Depth + 1, Q); 1978 FirstAnswer = std::min(Tmp, Tmp2); 1988 Tmp2 = ComputeNumSignBits(U->getOperand(2), DL, Depth + 1, Q); 1989 return std::min(Tmp, Tmp2); 2015 Tmp2 [all...] |
/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
H A D | structs.h | 252 double Tmp2[MAXFFTSIZE]; member in struct:__anon17042
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H A D | fft.c | 338 if (fftstate->Tmp0 == NULL || fftstate->Tmp1 == NULL || fftstate->Tmp2 == NULL || fftstate->Tmp3 == NULL 346 Cos = (REAL *) fftstate->Tmp2;
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 1511 SmallVector<MachineOperand,1> Tmp2; local 1519 Tmp2.clear(); 1520 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false); 1523 if (TB != Header && (Tmp2.empty() || FB != Header)) 1532 bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
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H A D | HexagonISelLowering.cpp | 1099 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]); local 1123 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2342 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 2343 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2346 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2357 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2486 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local 2487 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2494 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; local 2495 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 2496 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 2548 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp [all...] |
/external/llvm/lib/Support/ |
H A D | APInt.cpp | 799 uint16_t Tmp2 = uint16_t(VAL); 800 Tmp2 = ByteSwap_16(Tmp2); 801 return APInt(BitWidth, (uint64_t(Tmp2) << 32) | Tmp1);
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/external/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 774 llvm::Value *Tmp2 = Builder.CreateMul(LHSi, RHSi); // b*d local 775 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 1989 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1); local 1991 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2); 2005 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); local 2015 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2); 2082 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1, local 2084 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1698 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); local 1699 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 1758 SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); local 1759 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 1965 SDValue Tmp2 = ST->getBasePtr(); local 1972 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 500 SDValue Tmp1, Tmp2; local 2954 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local 2956 SDValue(Tmp2, 0)); 2968 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local 2970 SDValue(Tmp2, 0));
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H A D | PPCISelLowering.cpp | 6391 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); local 6393 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); 6420 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); local 6422 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); 6448 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); local 6450 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3112 unsigned Tmp2 = MRI.createVirtualRegister(RC); local 3113 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp); 3115 .addReg(Tmp2).addImm(-1);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 2724 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) local 2727 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
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H A D | ARMISelLowering.cpp | 4086 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); local 4087 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 4120 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); local 4123 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 4127 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); local 4133 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 4171 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); local 4174 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
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