/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeTypesGeneric.cpp | 375 EVT VecVT = N->getValueType(0); local 376 unsigned NumElts = VecVT.getVectorNumElements(); 381 assert(OldVT == VecVT.getVectorElementType() && 404 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec); 415 EVT VecVT = N->getValueType(0); local 416 unsigned NumElts = VecVT.getVectorNumElements(); 423 assert(OldEVT == VecVT.getVectorElementType() && 446 return DAG.getNode(ISD::BITCAST, dl, VecVT, NewVec);
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H A D | LegalizeVectorTypes.cpp | 827 EVT VecVT = Vec.getValueType(); local 828 EVT SubVecVT = VecVT.getVectorElementType(); 829 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 835 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 905 EVT VecVT = Vec.getValueType(); 906 EVT EltVT = VecVT.getVectorElementType(); 907 SDValue StackPtr = DAG.CreateStackTemporary(VecVT); 914 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext()); 1443 EVT VecVT = Vec.getValueType(); local 1447 assert(IdxVal < VecVT [all...] |
H A D | LegalizeFloatTypes.cpp | 1821 EVT VecVT = Vec->getValueType(0); local 1822 EVT EltVT = VecVT.getVectorElementType(); 1826 switch (getTypeAction(VecVT)) {
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H A D | LegalizeIntegerTypes.cpp | 998 EVT VecVT = N->getValueType(0); local 999 unsigned NumElts = VecVT.getVectorNumElements(); 1000 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
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H A D | DAGCombiner.cpp | 11249 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 11250 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 11253 if (!isTypeLegal(VecVT)) return SDValue(); 11256 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); 11565 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT, local 11568 DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Ops));
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2092 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, argument 2097 if (VecVT.isFloatingPoint()) { 2120 if (VecVT == MVT::v4f32) 2122 else if (VecVT == MVT::v2f64) 2127 if (VecVT == MVT::v4f32) 2129 else if (VecVT == MVT::v2f64) 2134 if (VecVT == MVT::v4f32) 2136 else if (VecVT == MVT::v2f64) 2164 if (VecVT == MVT::v16i8) 2166 else if (VecVT [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2150 EVT VecVT = Vec.getValueType(); local 2151 SDValue Width = DAG.getConstant(VecVT.getSizeInBits(), MVT::i64); 2159 if ((VecVT.getSimpleVT() == MVT::v2i16) && (NElts == 2) && W && S) { 2168 if ((VecVT.getSimpleVT() == MVT::v4i8) && (NElts == 2) && W && S) { 2209 EVT VecVT = Vec.getValueType(); local 2210 EVT EltVT = VecVT.getVectorElementType(); 2225 if (VecVT.getSimpleVT() == MVT::v2i32) { 2235 } else if ((VecVT.getSimpleVT() == MVT::v4i16) && 2246 } else if ((VecVT.getSimpleVT() == MVT::v8i8) && 2257 } else if (VecVT 2297 EVT VecVT = Vec.getValueType(); local [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 1531 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize); 1568 Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext())); 2196 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2); local 2198 VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM)); 2200 VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, 2202 TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext()))); 2234 EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize); local 2238 PointerType::get(VecVT.getTypeForEVT(F->getContext()), 2244 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false, 2246 TD->getABITypeAlignment(VecVT 2403 EVT VecVT = local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 2547 MVT VecVT = MVT::Other; local 2552 VecVT = MVT::v16f32; 2554 VecVT = MVT::v8f32; 2556 VecVT = MVT::v4f32; 2562 if (VecVT != MVT::Other) 2563 RegParmTypes.push_back(VecVT); 3875 MVT VecVT = N->getOperand(0).getSimpleValueType(); local 3876 MVT ElVT = VecVT.getVectorElementType(); 3890 MVT VecVT = N->getSimpleValueType(0); local 3891 MVT ElVT = VecVT 5688 EVT VecVT = MVT::v4i32; local 10573 MVT VecVT = Vec.getSimpleValueType(); local 12265 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); local 13456 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 3379 EVT VecVT; local 3385 VecVT = MVT::v4i32; 3389 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 3390 DAG.getUNDEF(VecVT), In1); 3391 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT, 3392 DAG.getUNDEF(VecVT), In2); 3394 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); 3395 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); 3399 VecVT = MVT::v2i64; 3407 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT, 5968 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts); local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 2799 EVT VecVT = N->getValueType(0); local 2800 EVT EltVT = VecVT.getVectorElementType(); 2801 unsigned NumElts = VecVT.getVectorNumElements(); 2804 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)); 2808 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1)); 2810 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
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H A D | ARMISelLowering.cpp | 5117 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); local 5118 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); 5150 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local 5154 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); 5604 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); local 5605 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 5606 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 5617 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); 8633 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); local 8636 if (!TLI.isTypeLegal(VecVT)) [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 928 EVT VecVT = Vector.getValueType(); local 929 EVT EltVT = VecVT.getVectorElementType(); 932 for (unsigned i = 0, e = VecVT.getVectorNumElements(); 938 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args);
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