/external/skia/src/gpu/gl/ |
H A D | GrGLSL_impl.h | 25 inline Self GrGLSLExpr<Self>::Mul(T0 in0, T1 in1) { function in class:GrGLSLExpr 100 return GrGLSLExpr1::Mul(in0, in1); 140 return GrGLSLExpr4::Mul(in0, in1); 152 return GrGLSLExpr4::Mul(in0, in1); 164 return GrGLSLExpr4::Mul(in0, in1);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 183 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue, local 186 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), local 52 SDValue InFlag = SDValue(Mul, 0); 293 /// Mul with two results
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/external/llvm/unittests/Transforms/Utils/ |
H A D | Cloning.cpp | 66 BinaryOperator *Mul = BinaryOperator::Create(Instruction::Mul, V, V); local 70 BinaryOperator *MulClone = this->clone(Mul); 83 Mul->setHasNoUnsignedWrap(); 87 MulClone = this->clone(Mul); 100 Mul->setHasNoSignedWrap(); 104 MulClone = this->clone(Mul); 117 Mul->setHasNoUnsignedWrap(false); 121 MulClone = this->clone(Mul);
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/external/llvm/lib/Transforms/Scalar/ |
H A D | StraightLineStrengthReduce.cpp | 85 Mul, // (B + i) * S enumerator in enum:__anon11093::StraightLineStrengthReduce::Candidate::Kind 164 // Allocate candidates and find bases for Mul instructions. 303 if (C.CandidateKind == Candidate::Mul) { 364 case Instruction::Mul: 414 allocateCandidatesAndFindBasis(Candidate::Mul, SE->getSCEV(B), Idx, RHS, I); 418 allocateCandidatesAndFindBasis(Candidate::Mul, SE->getSCEV(LHS), Zero, RHS, 601 case Candidate::Mul:
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H A D | Reassociate.cpp | 455 assert((Opcode == Instruction::Mul || Opcode == Instruction::FMul) && 694 if ((Opcode == Instruction::Mul && BinaryOperator::isNeg(BO)) || 1049 BinaryOperator *Mul = local 1052 Mul->takeName(Shl); 1055 Shl->replaceAllUsesWith(Mul); 1056 Mul->setDebugLoc(Shl->getDebugLoc()); 1064 Mul->setHasNoSignedWrap(true); 1065 Mul->setHasNoUnsignedWrap(NUW); 1066 return Mul; 1113 BinaryOperator *BO = isReassociableOp(V, Instruction::Mul, Instructio [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 199 BinaryOperator *Mul = cast<BinaryOperator>(I.getOperand(0)); local 201 if (I.hasNoUnsignedWrap() && Mul->hasNoUnsignedWrap()) 203 if (I.hasNoSignedWrap() && Mul->hasNoSignedWrap() && 273 Value *Mul = Builder->CreateMul(C1, Op1); local 276 if (!match(Mul, m_Mul(m_Value(), m_Value()))) 277 return BinaryOperator::CreateAdd(Builder->CreateMul(X, Op1), Mul); 824 Instruction::Mul, X, ConstantInt::get(X->getType(), Quotient)); 852 Instruction::Mul, X, ConstantInt::get(X->getType(), Quotient));
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H A D | InstCombineCompares.cpp | 1473 case Instruction::Mul: { // (icmp pred (mul X, Val), CI) 1861 case Instruction::Mul: 2244 assert(MulInstr->getOpcode() == Instruction::Mul); 2394 Value *Mul = Builder->CreateExtractValue(Call, 0, "umul.value"); local 2400 IC.ReplaceInstUsesWith(*TI, Mul); 2402 TI->setOperand(0, Mul); 2408 Value *ShortAnd = Builder->CreateAnd(Mul, ShortMask); 3450 case Instruction::Mul:
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/external/llvm/include/llvm/MC/ |
H A D | MCExpr.h | 412 Mul, ///< Multiplication. enumerator in enum:llvm::MCBinaryExpr::Opcode 480 return Create(Mul, LHS, RHS, Ctx);
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/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 893 /// SimplifyMulInst - Given operands for a Mul, see if we can 900 return ConstantFoldInstOperands(Instruction::Mul, CLHS->getType(), 932 if (Value *V = SimplifyAssociativeBinOp(Instruction::Mul, Op0, Op1, Q, 936 // Mul distributes over Add. Try some generic simplifications based on this. 937 if (Value *V = ExpandBinOp(Instruction::Mul, Op0, Op1, Instruction::Add, 944 if (Value *V = ThreadBinOpOverSelect(Instruction::Mul, Op0, Op1, Q, 951 if (Value *V = ThreadBinOpOverPHI(Instruction::Mul, Op0, Op1, Q, 1038 OverflowingBinaryOperator *Mul = cast<OverflowingBinaryOperator>(Op0); local 1039 // If the Mul knows it does not overflow, then we are good to go. 1040 if ((isSigned && Mul [all...] |
H A D | ScalarEvolution.cpp | 298 const SCEVMulExpr *Mul = dyn_cast<SCEVMulExpr>(this); local 299 if (!Mul) return false; 302 const SCEVConstant *SC = dyn_cast<SCEVConstant>(Mul->getOperand(0)); 1870 const SCEVMulExpr *Mul = dyn_cast<SCEVMulExpr>(Ops[i]); local 1871 if (Mul && isa<SCEVConstant>(Mul->getOperand(0))) { 1873 Scale * cast<SCEVConstant>(Mul->getOperand(0))->getValue()->getValue(); 1874 if (Mul->getNumOperands() == 2 && isa<SCEVAddExpr>(Mul->getOperand(1))) { 1876 const SCEVAddExpr *Add = cast<SCEVAddExpr>(Mul 2009 const SCEV *Mul = getMulExpr(Scale, Ops[i]); variable 2139 const SCEVMulExpr *Mul = cast<SCEVMulExpr>(Ops[Idx]); variable [all...] |
/external/llvm/lib/Target/R600/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 1160 static bool ConvertOmodMul(int64_t &Mul) { argument 1161 if (Mul != 1 && Mul != 2 && Mul != 4) 1164 Mul >>= 1;
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 1114 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0); local 1116 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul); 1146 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); local 1149 NegDivScale0, Mul, DivScale1); 1181 Fma4, Fma3, Mul, Scale);
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H A D | AMDGPUISelLowering.cpp | 1903 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y); local 1905 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); 2212 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0); local 2214 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul); 2382 SDValue Mul; local 2387 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1); 2391 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1); 2398 return DAG.getSExtOrTrunc(Mul, DL, VT);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 664 SDValue Mul; local 667 Mul = N->getOperand(0); 670 Mul = N->getOperand(1); 678 Mul.getOperand(0), DAG.getConstant(0, MVT::i32)); 680 Mul.getOperand(1), DAG.getConstant(0, MVT::i32)); 686 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); 687 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); 688 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && 689 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { 707 Mul [all...] |
/external/v8/src/arm64/ |
H A D | macro-assembler-arm64-inl.h | 985 void MacroAssembler::Mul(const Register& rd, function in class:v8::internal::MacroAssembler
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/external/valgrind/VEX/priv/ |
H A D | host_tilegx_defs.h | 394 } Mul; member in union:__anon15562::__anon15563
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H A D | host_mips_defs.h | 432 } Mul; member in union:__anon15340::__anon15341
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H A D | host_arm_defs.h | 745 } Mul; member in union:__anon15255::__anon15256
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/external/llvm/bindings/ocaml/llvm/ |
H A D | llvm.ml | 164 | Mul Constructor in type:Opcode/t
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/external/llvm/lib/Bitcode/Reader/ |
H A D | BitcodeReader.cpp | 618 return Ty->isFPOrFPVectorTy() ? Instruction::FMul : Instruction::Mul; member in class:__anon10384::BitcodeReaderValueList::Instruction 2273 Opc == Instruction::Mul || 3413 Opc == Instruction::Mul ||
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/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 3007 Value *Mul = EmitNeonCall(CGM.getIntrinsic(LLVMIntrinsic, Ty), local 3012 AccumOps.push_back(Mul);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 727 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS); local 735 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 741 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 742 Mul, DAG.getValueType(SmallVT)); 743 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 749 SDValue(Mul.getNode(), 1)); 753 return Mul;
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/external/v8/src/mips64/ |
H A D | macro-assembler-mips64.cc | 680 void MacroAssembler::Mul(Register rd, Register rs, const Operand& rt) { function in class:v8::internal::MacroAssembler
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/external/vixl/src/vixl/a64/ |
H A D | macro-assembler-a64.h | 1633 void Mul(const Register& rd, const Register& rn, const Register& rm) { function in class:vixl::MacroAssembler 2116 V(mul, Mul) \ 2331 V(mul, Mul) \
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