Searched refs:RC (Results 226 - 250 of 458) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsISelLowering.cpp692 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) argument
694 assert(RC->contains(PReg) && "Not the correct regclass!");
695 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
882 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
890 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
891 unsigned AndRes = RegInfo.createVirtualRegister(RC);
892 unsigned Success = RegInfo.createVirtualRegister(RC);
955 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
963 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
964 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1107 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
1175 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
2279 TargetRegisterClass *RC = 0; local
2388 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; local
[all...]
/external/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp105 const TargetRegisterClass *RC,
122 if (RC->hasType(MVT::i8)) {
124 } else if (RC->hasType(MVT::i16)) {
140 const TargetRegisterClass *RC,
156 if (RC->hasType(MVT::i8)) {
158 } else if (RC->hasType(MVT::i16)) {
101 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
137 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DAVRRegisterInfo.cpp79 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
81 if (RC->hasType(MVT::i16)) {
85 if (RC->hasType(MVT::i8)) {
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DStackSlotColoring.cpp142 unsigned Reg, const TargetRegisterClass *RC,
275 const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS); local
278 if (!RC) {
282 unsigned Reg = VRM->getFirstUnusedRegister(RC);
421 const TargetRegisterClass *RC = LS->getIntervalRegClass(SS); local
430 UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
524 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI); local
525 if (RC && !RC->contains(NewReg))
586 const TargetRegisterClass *RC local
610 UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI, unsigned Reg, const TargetRegisterClass *RC, SmallSet<unsigned, 4> &Defs, MachineFunction &MF) argument
[all...]
H A DAggressiveAntiDepBreaker.h44 /// RC - The register class
45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon18507
/external/llvm/lib/Target/AArch64/
H A DAArch64RegisterBankInfo.cpp80 const TargetRegisterClass &RC) const {
81 switch (RC.getID()) {
/external/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp86 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local
87 if (RC == &AMDGPU::VReg_1RegClass)
H A DR600MachineScheduler.h86 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
H A DR600RegisterInfo.cpp76 const TargetRegisterClass *RC) const {
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h69 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegColoring.cpp139 const TargetRegisterClass *RC = MRI->getRegClass(Old); local
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp246 for (const auto &RC : getRegBank().getRegClasses()) {
247 if (RC.contains(Reg)) {
248 ArrayRef<MVT::SimpleValueType> InVTs = RC.getValueTypes();
261 for (const auto &RC : getRegBank().getRegClasses())
262 LegalValueTypes.insert(LegalValueTypes.end(), RC.VTs.begin(), RC.VTs.end());
429 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, argument
431 std::vector<Record*> Defs = RC.getAllDerivedDefinitions("Intrinsic");
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
H A DMBlazeInstrInfo.h218 const TargetRegisterClass *RC,
224 const TargetRegisterClass *RC,
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp931 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) argument
933 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1110 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); local
1146 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1147 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1148 unsigned Success = RegInfo.createVirtualRegister(RC);
1214 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
1215 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1234 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
1246 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1398 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); local
1488 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); local
3432 const TargetRegisterClass *RC; local
3753 const TargetRegisterClass *RC = getRegClassFor(RegTy); local
3875 const TargetRegisterClass *RC = getRegClassFor(RegTy); local
[all...]
H A DMips16ISelDAGToDAG.cpp77 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
79 V0 = RegInfo.createVirtualRegister(RC);
80 V1 = RegInfo.createVirtualRegister(RC);
81 V2 = RegInfo.createVirtualRegister(RC);
/external/llvm/include/llvm/CodeGen/
H A DLiveStackAnalysis.h58 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DLiveStackAnalysis.h57 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
H A DRegisterScavenging.h103 BitVector getRegsAvailable(const TargetRegisterClass *RC);
/external/llvm/include/llvm/Analysis/
H A DCGSCCPassManager.h101 for (LazyCallGraph::RefSCC &RC : CG.postorder_ref_sccs()) {
103 dbgs() << "Running an SCC pass across the RefSCC: " << RC << "\n";
105 for (LazyCallGraph::SCC &C : RC) {
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp182 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; local
183 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
191 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument
193 const TargetRegisterClass *Super = RC;
194 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
208 return RC;
218 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
219 if (RC == &ARM::CCRRegClass)
221 return RC;
225 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument
[all...]
H A DARMFastISel.cpp105 const TargetRegisterClass *RC,
108 const TargetRegisterClass *RC,
112 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
121 const TargetRegisterClass *RC,
279 const TargetRegisterClass *RC,
281 unsigned ResultReg = createResultReg(RC);
301 const TargetRegisterClass *RC,
304 unsigned ResultReg = createResultReg(RC);
329 const TargetRegisterClass *RC,
278 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
300 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
328 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
354 fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
384 fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
481 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
497 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : local
550 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
679 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); local
853 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
924 const TargetRegisterClass *RC; local
1482 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass local
1652 const TargetRegisterClass *RC; local
2480 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass local
2671 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; local
3039 const TargetRegisterClass *RC = &ARM::rGPRRegClass; local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp57 const TargetRegisterClass *RC) const {
78 switch (RC->getID()) {
97 dbgs() << "Register class: " << getRegClassName(RC) << "\n";
H A DHexagonGenInsert.cpp485 bool isIntClass(const TargetRegisterClass *RC) const;
595 inline bool HexagonGenInsert::isIntClass(const TargetRegisterClass *RC) const {
596 return RC == &Hexagon::IntRegsRegClass || RC == &Hexagon::DoubleRegsRegClass;
601 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
602 uint16_t W = RC.width();
604 const BitTracker::BitValue &BV = RC[i];
614 const BitTracker::RegisterCell &RC = CMS->lookup(VR);
615 uint16_t W = RC.width();
620 const BitTracker::BitValue &BV = RC[
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h195 const TargetRegisterClass *RC,
200 const TargetRegisterClass *RC,
232 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
/external/llvm/lib/Target/X86/
H A DX86VZeroUpper.cpp274 const TargetRegisterClass *RC = &X86::VR256RegClass; local
275 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;

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