/external/opencv/cxcore/src/ |
H A D | cxmatrix.cpp | 289 const arrtype* src1 = src + srcstep; \ 296 arrtype t1 = src1[x]; \ 302 t1 = src1[x + 1]; \ 310 arrtype t1 = src1[x]; \
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H A D | cxnorm.cpp | 92 worktype t0 = (src1)[x] - (src2)[x];\ 93 worktype t1 = (src1)[x+1]-(src2)[x+1];\ 101 t0 = (src1)[x+2] - (src2)[x+2]; \ 102 t1 = (src1)[x+3] - (src2)[x+3]; \ 113 worktype t0 = (src1)[x] - (src2)[x];\ 122 worktype t0 = (src1)[x*(cn)] - (src2)[x*(cn)]; \ 278 IPCVAPI_IMPL( CvStatus, name,( const arrtype* src1, int step1, \ 280 (src1, step1, src2, step2, size, _norm)) \ 285 step1 /= sizeof(src1[0]); \ 288 for( ; size.height--; src1 [all...] |
/external/mesa3d/src/gallium/state_trackers/nine/ |
H A D | nine_shader.c | 774 struct ureg_src src1, INT idx) 784 ureg_TEX(tx->ureg, dst, target, src0, src1); 786 ureg_TXP(tx->ureg, dst, target, src0, src1); 790 ureg_TEX(tx->ureg, dst, target, ureg_src(tmp), src1); 1588 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); local 1590 ureg_ADD(ureg, dst, src0, ureg_negate(src1)); 2735 struct ureg_src src1 = tx_src_param(tx, &tx->insn.src[1]); local 2751 /* dest.r = src0.r + D3DTSS_BUMPENVMAT00(stage n) * src1.r */ 2753 NINE_APPLY_SWIZZLE(src1, X), NINE_APPLY_SWIZZLE(src0, X)); 2754 /* dest.r = dest.r + D3DTSS_BUMPENVMAT10(stage n) * src1 772 TEX_with_ps1x_projection(struct shader_translator *tx, struct ureg_dst dst, unsigned target, struct ureg_src src0, struct ureg_src src1, INT idx) argument [all...] |
/external/mesa3d/src/intel/blorp/ |
H A D | blorp_blit.c | 1325 GLfloat src0, GLfloat src1, 1329 double scale = (double)(src1 - src0) / (double)(dst1 - dst0); 1536 double src0, src1, dst0, dst1; member in struct:blt_axis 1655 coords->x.src0, coords->x.src1, 1659 coords->y.src0, coords->y.src1, 1850 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the 1852 * delta1, and src1 is adjusted by delta0. 1857 split_coords->src1 = orig->src1 + (scale >= 0.0 ? delta1 : delta0); 1924 shrink_surface_params(dev, ¶ms->src, &coords->x.src0, &coords->x.src1, 1324 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform, GLfloat src0, GLfloat src1, GLfloat dst0, GLfloat dst1, bool mirror) argument [all...] |
/external/mesa3d/src/intel/vulkan/ |
H A D | anv_blorp.c | 392 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1) argument 395 if (*src0 > *src1) { 397 *src0 = *src1; 398 *src1 = tmp;
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H A D | anv_nir_apply_dynamic_offsets.c | 110 nir_phi_src *src1 = ralloc(phi, nir_phi_src); local 112 src1->pred = exec_node_data(nir_block, tnode, cf_node.node); 113 src1->src = nir_src_for_ssa(&intrin->dest.ssa); 114 exec_list_push_tail(&phi->srcs, &src1->node);
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
H A D | i915_fragprog.c | 419 GLuint src0, src1, src2, flags; local 438 src1 = src_vector(p, &inst->SrcReg[1], program); 440 i915_emit_arith(p, A0_CMP, get_result_vector(p, inst), get_result_flags(inst), 0, src0, src2, src1); /* NOTE: order of src2, src1 */ 524 src1 = src_vector(p, &inst->SrcReg[1], program); 530 swizzle(src1, X, Y, ZERO, ZERO), 544 src1 = src_vector(p, &inst->SrcReg[1], program); 550 swizzle(src0, X, Y, Z, ONE), src1, 0); 555 src1 = src_vector(p, &inst->SrcReg[1], program); 567 swizzle(src1, ON [all...] |
H A D | i915_program.c | 144 GLuint saturate, GLuint src0, GLuint src1, GLuint src2) 155 if (GET_UREG_TYPE(src1) == REG_TYPE_CONST) 169 s[1] = src1; 185 src1 = s[1]; 196 *(p->csr++) = (A1_SRC0(src0) | A1_SRC1(src1)); 197 *(p->csr++) = (A2_SRC1(src1) | A2_SRC2(src2)); 140 i915_emit_arith(struct i915_fragment_program * p, GLuint op, GLuint dest, GLuint mask, GLuint saturate, GLuint src0, GLuint src1, GLuint src2) argument
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H A D | i915_program.h | 125 GLuint src0, GLuint src1, GLuint src2);
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_disasm.c | 1132 src1(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst) function 1330 err |= src1(file, devinfo, inst); 1356 err |= src1(file, devinfo, inst); 1366 err |= src1(file, devinfo, inst);
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H A D | brw_eu.h | 140 struct brw_reg src1); 146 struct brw_reg src1, \ 332 struct brw_reg src1); 393 struct brw_reg src0, struct brw_reg src1); 426 struct brw_reg src1);
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H A D | brw_eu_emit.c | 360 * is an immediate that src1's type must be the same as that of src0. 375 * immediate in src0 use a:ud for src1. 381 * Don't do any of this for 64-bit immediates, since the src1 fields 402 * Strangely, we do have a mapping for imm:f in src1, so we don't need 500 /* Only src1 can be immediate in two-argument instructions. 845 struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) 849 assert(src1.file != BRW_IMMEDIATE_VALUE || type_sz(src1.type) <= 4); 854 brw_set_src1(p, insn, src1); 870 struct brw_reg src0, struct brw_reg src1, struc 844 brw_alu2(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) argument 869 brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) argument 1097 brw_AVG(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) argument 1118 brw_MUL(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) argument 1152 brw_LINE(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) argument 1162 brw_PLN(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0, struct brw_reg src1) argument 1387 gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional, struct brw_reg src0, struct brw_reg src1) argument 1895 brw_CMP(struct brw_codegen *p, struct brw_reg dest, unsigned conditional, struct brw_reg src0, struct brw_reg src1) argument 1964 gen6_math(struct brw_codegen *p, struct brw_reg dest, unsigned function, struct brw_reg src0, struct brw_reg src1) argument [all...] |
H A D | brw_fs.cpp | 115 const fs_reg &src0, const fs_reg &src1) 117 const fs_reg src[2] = { src0, src1 }; 122 const fs_reg &src0, const fs_reg &src1, const fs_reg &src2) 124 const fs_reg src[3] = { src0, src1, src2 }; 800 /* The payload is actually stored in src1 */ 3359 * src1 are used. 3476 * FINISHME: Don't use source modifiers on src1. 4310 const fs_reg src1 = is_int_div ? inst->src[0] : inst->src[1]; 4316 bld.MOV(fs_reg(MRF, inst->base_mrf + 1, src1.type), src1); 114 fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, const fs_reg &src0, const fs_reg &src1) argument 121 fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst, const fs_reg &src0, const fs_reg &src1, const fs_reg &src2) argument [all...] |
H A D | brw_fs.h | 443 struct brw_reg src1);
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H A D | brw_fs_builder.h | 304 const src_reg &src1) const 312 fix_math_operand(src1))); 315 return emit(instruction(opcode, dispatch_width(), dst, src0, src1)); 325 const src_reg &src1, const src_reg &src2) const 334 fix_3src_operand(src1), 339 src0, src1, src2)); 379 * conditional mod evaluates to true, otherwise select \p src1. 385 const src_reg &src1, brw_conditional_mod mod) const 390 fix_unsigned_negate(src1))); 429 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) cons 324 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const argument 384 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument 507 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument [all...] |
H A D | brw_fs_generator.cpp | 548 * | src1+0 | src1+1 | src1+2 | src1+3 | 556 * | src1+0 | src1+1 | src1+2 | src1+3 | 1008 struct brw_reg src1 = brw_reg(src.file, src.nr, 0, local 1015 brw_ADD(p, dst, src0, negate(src1)); 1035 struct brw_reg src1 = brw_reg(src.file, src.nr, 0, local 1055 struct brw_reg src1 = brw_reg(src.file, src.nr, 2, local 1390 generate_set_sample_id(fs_inst *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument [all...] |
H A D | brw_fs_nir.cpp | 3591 const fs_reg src1 = (info->num_srcs >= 3 3602 src1, 1, 1, 3648 const fs_reg src1 = (info->num_srcs >= 4 ? 3662 tmp = emit_image_atomic(bld, image, addr, src0, src1,
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H A D | brw_fs_surface_builder.cpp | 97 const fs_reg &src0, const fs_reg &src1, 104 const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE); 105 const fs_reg srcs[] = { src0, src1 }; 148 const fs_reg &src0, const fs_reg &src1, 155 const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE); 156 const fs_reg srcs[] = { src0, src1 }; 1165 const fs_reg &src0, const fs_reg &src1, 1184 const fs_reg tmp = emit_typed_atomic(bld, image, saddr, src0, src1, 95 emit_untyped_atomic(const fs_builder &bld, const fs_reg &surface, const fs_reg &addr, const fs_reg &src0, const fs_reg &src1, unsigned dims, unsigned rsize, unsigned op, brw_predicate pred) argument 146 emit_typed_atomic(const fs_builder &bld, const fs_reg &surface, const fs_reg &addr, const fs_reg &src0, const fs_reg &src1, unsigned dims, unsigned rsize, unsigned op, brw_predicate pred) argument 1163 emit_image_atomic(const fs_builder &bld, const fs_reg &image, const fs_reg &addr, const fs_reg &src0, const fs_reg &src1, unsigned surf_dims, unsigned arr_dims, unsigned rsize, unsigned op) argument
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H A D | brw_fs_surface_builder.h | 48 const fs_reg &src0, const fs_reg &src1, 64 const fs_reg &src0, const fs_reg &src1, 84 const fs_reg &src0, const fs_reg &src1,
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H A D | brw_inst.h | 661 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96) 694 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
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H A D | brw_ir_fs.h | 332 const fs_reg &src0, const fs_reg &src1); 334 const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
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H A D | brw_ir_vec4.h | 273 const src_reg &src1 = src_reg(),
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H A D | brw_vec4.h | 178 const src_reg &src0, const src_reg &src1); 180 const src_reg &src0, const src_reg &src1, 211 vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1, 213 vec4_instruction *IF(src_reg src0, src_reg src1, 238 src_reg src0, src_reg src1); 253 const src_reg &src1 = src_reg());
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H A D | brw_vec4_builder.h | 270 const src_reg &src1) const 279 fix_math_operand(src1)))); 282 return emit(instruction(opcode, dst, src0, src1)); 291 const src_reg &src1, const src_reg &src2) const 300 fix_3src_operand(src1), 304 return emit(instruction(opcode, dst, src0, src1, src2)); 331 * conditional mod evaluates to true, otherwise select \p src1. 337 const src_reg &src1, brw_conditional_mod mod) const 342 fix_unsigned_negate(src1))); 375 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) cons 290 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const argument 336 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument 453 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument 487 IF(const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument [all...] |
H A D | brw_vec4_generator.cpp | 58 struct brw_reg src1) 64 if (src1.file == BRW_GENERAL_REGISTER_FILE) 65 check_gen6_math_src_arg(src1); 68 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1); 77 struct brw_reg src1) 89 struct brw_reg &op0 = is_int_div ? src1 : src0; 90 struct brw_reg &op1 = is_int_div ? src0 : src1; 418 struct brw_reg src1) 432 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst. 436 * mul(2) dst.3<1>UD src0<8;2,4>UD src1< 54 generate_math_gen6(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument 73 generate_math2_gen4(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument 415 generate_gs_set_write_offset(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument 490 generate_gs_svb_write(struct brw_codegen *p, struct brw_vue_prog_data *prog_data, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument 659 generate_gs_ff_sync_set_primitives(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1, struct brw_reg src2) argument 681 generate_gs_ff_sync(struct brw_codegen *p, vec4_instruction *inst, struct brw_reg dst, struct brw_reg src0, struct brw_reg src1) argument [all...] |