| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 195 case ISD::ADDE: {
199 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
204 if (Opcode == ISD::ADDE) {
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| H A D | MipsSEISelDAGToDAG.cpp | 245 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
739 case ISD::ADDE: {
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsISelDAGToDAG.cpp | 210 case ISD::ADDE: {
213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
218 if (Opcode == ISD::ADDE) {
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| H A D | MipsISelLowering.cpp | 217 setTargetDAGCombine(ISD::ADDE);
644 case ISD::ADDE:
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| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 123 case ISD::ADDE:
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 217 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 907 case ISD::ADDE: return true;
|
| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativePPC_32.c | 124 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)));
127 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
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| H A D | sljitNativePPC_64.c | 245 FAIL_IF(push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2)));
249 return push_inst(compiler, ADDE | D(dst) | A(src1) | B(src2));
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 223 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 1185 case ISD::ADDE:
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| H A D | BlackfinISelLowering.cpp | 98 setOperationAction(ISD::ADDE, MVT::i32, Custom);
422 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
471 case ISD::ADDE:
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 75 ADDE, // Add using carry enumerator in enum:llvm::ARMISD::NodeType
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 72 ADDE, // Add using carry
|
| H A D | ARMISelLowering.cpp | 745 setOperationAction(ISD::ADDE, MVT::i32, Custom);
1147 case ARMISD::ADDE: return "ARMISD::ADDE";
6900 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
7207 case ISD::ADDE:
8825 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8830 // loAdd -> ADDE |
8858 // Look for the glued ADDE.
8863 // Make sure it is really an ADDE
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 227 case ISD::ADDE: return "adde";
|
| H A D | LegalizeIntegerTypes.cpp | 1390 case ISD::ADDE:
1736 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1738 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1751 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1832 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 91 setOperationAction(ISD::ADDE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 99 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1834 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1835 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1836 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1837 setOperationAction(ISD::ADDE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1614 setOperationAction(ISD::ADDE, MVT::i64, Custom);
2929 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2930 case ISD::ADDE: hasChain = true; break;
3078 case ISD::ADDE:
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1145 case ISD::ADDE:
1284 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1512 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1514 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1527 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1576 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
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| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| H A D | AlphaISelLowering.cpp | 103 setOperationAction(ISD::ADDE , MVT::i64, Expand);
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 94 setOperationAction(ISD::ADDE, MVT::i32, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 317 case ISD::ADDE:
|