| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 605 // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
607 ATOMIC_LOAD, enumerator in enum:llvm::ISD::NodeType
609 // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val)
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| H A D | SelectionDAGNodes.h | 979 N->getOpcode() == ISD::ATOMIC_LOAD ||
1064 N->getOpcode() == ISD::ATOMIC_LOAD ||
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 700 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
702 ATOMIC_LOAD, enumerator in enum:llvm::ISD::NodeType
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| H A D | RuntimeLibcalls.h | 406 ATOMIC_LOAD, enumerator in enum:llvm::RTLIB::Libcall
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| H A D | SelectionDAGNodes.h | 1113 N->getOpcode() == ISD::ATOMIC_LOAD ||
1194 N->getOpcode() == ISD::ATOMIC_LOAD ||
|
| /external/v8/src/compiler/ |
| H A D | machine-operator.cc | 574 #define ATOMIC_LOAD(Type) \ macro
584 ATOMIC_TYPE_LIST(ATOMIC_LOAD)
585 #undef ATOMIC_LOAD macro
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 158 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
225 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
969 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 77 case ISD::ATOMIC_LOAD: return "AtomicLoad";
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| H A D | LegalizeIntegerTypes.cpp | 139 case ISD::ATOMIC_LOAD:
1335 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
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| H A D | SelectionDAG.cpp | 476 case ISD::ATOMIC_LOAD:
4893 if (Opcode != ISD::ATOMIC_LOAD)
4934 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
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| H A D | LegalizeDAG.cpp | 2791 case ISD::ATOMIC_LOAD: {
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1650 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1656 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
3083 case ISD::ATOMIC_LOAD:
|
| /external/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 1313 RTLIB::ATOMIC_LOAD, RTLIB::ATOMIC_LOAD_1, RTLIB::ATOMIC_LOAD_2,
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| H A D | TargetLoweringBase.cpp | 417 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load";
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| H A D | AlphaISelLowering.cpp | 157 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 239 setTargetDAGCombine(ISD::ATOMIC_LOAD);
3005 case ISD::ATOMIC_LOAD:
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 121 case ISD::ATOMIC_LOAD:
1116 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
|
| H A D | SelectionDAG.cpp | 436 case ISD::ATOMIC_LOAD:
4001 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
5888 case ISD::ATOMIC_LOAD: return "AtomicLoad";
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| H A D | LegalizeDAG.cpp | 3016 case ISD::ATOMIC_LOAD: {
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 198 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 170 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
172 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
4533 case ISD::ATOMIC_LOAD:
5304 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
5423 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 611 Use->getOpcode() != ISD::ATOMIC_LOAD &&
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 391 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 369 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 882 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
884 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
7215 case ISD::ATOMIC_LOAD:
|