| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 196 // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
198 SDIVREM, UDIVREM, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 202 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
204 SDIVREM, UDIVREM, enumerator in enum:llvm::ISD::NodeType
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| H A D | BlackfinISelLowering.cpp | 87 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
88 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 185 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
191 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
197 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
203 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
209 setOperationAction(ISD::UDIVREM, MVT::i128, Expand);
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 147 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
153 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
160 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 187 case ISD::UDIVREM: return "udivrem";
|
| H A D | LegalizeIntegerTypes.cpp | 2634 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2635 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
2660 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
2661 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
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| H A D | LegalizeVectorOps.cpp | 270 case ISD::UDIVREM:
|
| H A D | LegalizeDAG.cpp | 3235 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3254 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3967 case ISD::UDIVREM:
|
| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 81 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 683 case ISD::UDIVREM: {
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 301 setOperationAction(ISD::UDIVREM, VT, Custom);
386 setOperationAction(ISD::UDIVREM, VT, Expand);
710 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
1359 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1571 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
|
| H A D | MipsISelLowering.cpp | 422 setTargetDAGCombine(ISD::UDIVREM);
846 case ISD::UDIVREM:
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| H A D | MBlazeISelLowering.cpp | 104 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 95 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 718 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 818 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
820 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
823 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
7219 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
7254 case ISD::UDIVREM:
12009 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
12027 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
12051 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 220 setTargetDAGCombine(ISD::UDIVREM);
649 case ISD::UDIVREM:
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 3450 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3478 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3513 case ISD::UDIVREM:
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
330 setOperationAction(ISD::UDIVREM, VT, Expand);
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1961 case ISD::UDIVREM: {
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1879 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1937 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
|