Searched refs:src1 (Results 1 - 25 of 339) sorted by last modified time

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/external/wpa_supplicant_8/hostapd/src/utils/
H A D	common.c	724 const u8 *src1, size_t src1_len, 731 if (src1) { 733 os_memcpy(res, src1, res_len); 737 os_memcpy(res, src1, src1_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
H A D	common.h	507 const u8 *src1, size_t src1_len,
/external/wpa_supplicant_8/src/utils/
H A D	common.c	724 const u8 *src1, size_t src1_len, 731 if (src1) { 733 os_memcpy(res, src1, res_len); 737 os_memcpy(res, src1, src1_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
H A D	common.h	507 const u8 *src1, size_t src1_len,
/external/wpa_supplicant_8/wpa_supplicant/src/utils/
H A D	common.c	724 const u8 *src1, size_t src1_len, 731 if (src1) { 733 os_memcpy(res, src1, res_len); 737 os_memcpy(res, src1, src1_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
H A D	common.h	507 const u8 *src1, size_t src1_len,
/external/webrtc/webrtc/modules/video_processing/util/
H A D	denoiser_filter_sse2.cc	34 const __m128i src1 = _mm_unpacklo_epi8( local 38 const __m128i diff1 = _mm_sub_epi16(src1, ref1);
/external/webp/src/dsp/
H A D	dsp.h	306 typedef double (*VP8SSIMGetClippedFunc)(const uint8_t* src1, int stride1, 313 // 8 rows at offset src1 and src2 314 typedef double (*VP8SSIMGetFunc)(const uint8_t* src1, int stride1, 322 typedef uint32_t (*VP8AccumulateSSEFunc)(const uint8_t* src1,
H A D	enc_msa.c	86 v16u8 srcl0, srcl1, src0 = { 0 }, src1 = { 0 }; local 97 INSERT_W4_UB(in0, in1, in2, in3, src1); 98 ILVRL_B2_UB(src0, src1, srcl0, srcl1); 717 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 721 LD_UB8(a, BPS, src0, src1, src2, src3, src4, src5, src6, src7); 723 PACK_DOTP_UB4_SW(src0, ref0, src1, ref1, out0, out1, out2, out3); 729 LD_UB8(a, BPS, src0, src1, src2, src3, src4, src5, src6, src7); 731 PACK_DPADD_UB4_SW(src0, ref0, src1, ref1, out0, out1, out2, out3); 744 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 748 LD_UB8(a, BPS, src0, src1, src 763 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local 783 uint32_t src0, src1, src2, src3, ref0, ref1, ref2, ref3; local [all...]
H A D	enc_sse2.c	300 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); local 308 const __m128i src_0 = _mm_unpacklo_epi16(src0, src1); 345 const __m128i src1 = _mm_loadl_epi64((const __m128i*)&src[1 * BPS]); local 349 const __m128i src_1 = _mm_unpacklo_epi8(src1, zero); 391 const __m128i src1 = _mm_loadl_epi64((__m128i*)&in[1 * 16]); local 394 const __m128i A01 = _mm_unpacklo_epi16(src0, src1); // A0 A1 | ...
H A D	filters_msa.c	28 v16u8 src1, pred1, dst1; local 29 LD_UB2(src, 16, src0, src1); 31 SUB2(src0, pred0, src1, pred1, dst0, dst1);
H A D	lossless_enc_msa.c	21 #define TRANSFORM_COLOR_8(src0, src1, dst0, dst1, c0, c1, mask0, mask1) do { \ 24 VSHF_B2_SH(src0, src0, src1, src1, mask0, mask0, g0, g1); \ 28 t1 = __msa_subv_h((v8i16)src1, t1); \ 30 t5 = __msa_srli_w((v4i32)src1, 16); \ 34 VSHF_B2_UB(src0, t0, src1, t1, mask1, mask1, dst0, dst1); \ 63 v16u8 src1, dst1; local 64 LD_UB2(data, 4, src0, src1); 65 TRANSFORM_COLOR_8(src0, src1, dst0, dst1, g2br, r2b, mask0, mask1); 106 v16u8 src1, dst local [all...]
H A D	lossless_msa.c	25 v16u8 src0, src1, src2, src3, dst0, dst1, dst2; \ 26 LD_UB4(psrc, 16, src0, src1, src2, src3); \ 27 VSHF_B2_UB(src0, src1, src1, src2, m0, m1, dst0, dst1); \ 35 v16u8 src0, src1, src2, dst0, dst1, dst2; \ 36 LD_UB3(psrc, 16, src0, src1, src2); \ 37 VSHF_B2_UB(src0, src1, src1, src2, m0, m1, dst0, dst1); \ 46 v16u8 src0, src1, src2 = { 0 }, dst0, dst1; \ 47 LD_UB2(psrc, 16, src0, src1); \ 121 v16u8 src1, dst1; local 257 v16u8 src1, dst1, tmp1; local 302 v16u8 src1, dst1; local [all...]
H A D	rescaler_mips32.c	37 const uint8_t* src1 = src + channel; local 54 "lbu %[base], 0(%[src1]) \n\t" 56 "addu %[src1], %[src1], %[x_stride] \n\t" 71 : [accum]"=&r"(accum), [src1]"+r"(src1), [temp3]"=&r"(temp3), 97 const uint8_t* src1 = src + channel; local 106 "lbu %[temp2], 0(%[src1]) \n\t" 107 "addu %[src1], %[src1], [all...]
H A D	rescaler_msa.c	124 v4u32 src0, src1, src2, src3; local 126 LD_UW4(frow, 4, src0, src1, src2, src3); 127 CALC_MULT_FIX_16(src0, src1, src2, src3, scale, shift, out); 137 v4u32 src0, src1, src2; local 138 LD_UW3(frow, 4, src0, src1, src2); 140 CALC_MULT_FIX_4(src1, scale, shift, val1_m); 148 v4u32 src0, src1; local 149 LD_UW2(frow, 4, src0, src1); 151 CALC_MULT_FIX_4(src1, scale, shift, val1_m); 275 v4u32 src0, src1, src local 295 v4u32 src0, src1, src2, frac0, frac1, frac2; local 313 v4u32 src0, src1, frac0, frac1; local 360 v4u32 src0, src1, src2, src3; local 374 v4u32 src0, src1, src2; local 386 v4u32 src0, src1; local [all...]
H A D	ssim.c	63 static double SSIMGetClipped_C(const uint8_t* src1, int stride1, argument 74 src1 += ymin * stride1; 76 for (y = ymin; y <= ymax; ++y, src1 += stride1, src2 += stride2) { 80 const uint32_t s1 = src1[x]; 93 static double SSIMGet_C(const uint8_t* src1, int stride1, argument 97 for (y = 0; y <= 2 * VP8_SSIM_KERNEL; ++y, src1 += stride1, src2 += stride2) { 100 const uint32_t s1 = src1[x]; 117 static uint32_t AccumulateSSE_C(const uint8_t* src1, argument 123 const int32_t diff = src1[i] - src2[i];
H A D	ssim_sse2.c	45 static uint32_t AccumulateSSE_SSE2(const uint8_t* src1, argument 54 __m128i a0 = _mm_loadu_si128((const __m128i*)&src1[i]); 58 const __m128i a1 = _mm_loadu_si128((const __m128i*)&src1[i]); 64 a0 = _mm_loadu_si128((const __m128i*)&src1[i]); 77 const int32_t diff = src1[i] - src2[i]; 108 const __m128i a0 = _mm_loadl_epi64((const __m128i*)src1); \ 121 src1 += stride1; \ 125 static double SSIMGet_SSE2(const uint8_t* src1, int stride1, argument
/external/webp/src/enc/
H A D	picture_csp_enc.c	280 static void UpdateChroma(const fixed_y_t* src1, const fixed_y_t* src2, argument 284 const int r = ScaleDown(src1[0 * uv_w + 0], src1[0 * uv_w + 1], 286 const int g = ScaleDown(src1[2 * uv_w + 0], src1[2 * uv_w + 1], 288 const int b = ScaleDown(src1[4 * uv_w + 0], src1[4 * uv_w + 1], 295 src1 += 2; 478 fixed_y_t* const src1 = tmp_buffer + 0 * w; local 482 ImportOneRow(r_ptr, g_ptr, b_ptr, step, picture->width, src1); 516 fixed_y_t* const src1 = tmp_buffer + 0 * w; local [all...]
/external/vixl/src/aarch64/
H A D	logic-aarch64.cc	712 const LogicVRegister& src1, 717 int64_t sa = src1.Int(vform, i); 719 uint64_t ua = src1.Uint(vform, i); 756 const LogicVRegister& src1, 761 return cmp(vform, dst, src1, imm_reg, cond); 767 const LogicVRegister& src1, 771 uint64_t ua = src1.Uint(vform, i); 781 const LogicVRegister& src1, 787 uint64_t ua = src1.UintLeftJustified(vform, i); 812 const LogicVRegister& src1, 710 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 754 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) argument 765 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 779 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 810 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 822 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 833 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 844 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 856 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 867 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 878 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 889 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 901 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 913 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 925 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 937 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 949 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 961 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 973 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 985 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 997 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1009 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1021 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1033 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1045 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1057 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1069 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1081 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1093 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1105 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1116 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 1139 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1153 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1169 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1186 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1217 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1229 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1241 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1253 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1265 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1294 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1310 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1326 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1342 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1363 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1371 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1379 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1407 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1415 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1522 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1543 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1551 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1559 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument 1587 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1595 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1910 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 1970 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2217 absdiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) argument 2238 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2250 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2401 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 2843 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2855 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2867 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2878 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2889 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2901 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2913 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2924 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2935 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2947 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2959 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2970 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2981 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 2993 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3005 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3016 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3027 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3039 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3051 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3063 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3075 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3087 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3099 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3111 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3123 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3135 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3147 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3159 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3171 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3183 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3195 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3207 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3219 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3231 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3243 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3255 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3267 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3277 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3287 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3297 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3307 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3317 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3327 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) argument 3357 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3365 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3370 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3376 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3387 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3392 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3398 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3409 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3414 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3420 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3431 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3436 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local 3442 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3453 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3473 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3493 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3513 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3533 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3552 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3967 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3978 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 3993 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4008 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4023 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4038 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4077 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4109 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument 4130 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4146 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4161 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4177 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4247 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument 4351 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4371 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4391 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument 4411 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument [all...]
H A D	macro-assembler-aarch64.cc	1951 const CPURegister& src1, 1955 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 1958 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); 1962 PushHelper(count, size, src0, src1, src2, src3); 2006 const CPURegister& src1 = registers.PopLowestIndex(); local 2007 if (src1.IsValid()) { 2008 Stp(src0, src1, MemOperand(StackPointer(), offset)); 2078 const CPURegister& src1, 2087 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); 2094 VIXL_ASSERT(src1 1950 Push(const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument 2075 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument [all...]
H A D	macro-assembler-aarch64.h	814 const CPURegister& src1 = NoReg, 3154 const CPURegister& src1,
H A D	simulator-aarch64.h	1999 const LogicVRegister& src1, 2004 const LogicVRegister& src1, 2009 const LogicVRegister& src1, 2013 const LogicVRegister& src1, 2017 const LogicVRegister& src1, 2021 const LogicVRegister& src1, 2025 const LogicVRegister& src1, 2029 const LogicVRegister& src1, 2033 const LogicVRegister& src1, 2038 const LogicVRegister& src1, [all...]
/external/vixl/test/aarch32/
H A D	test-assembler-aarch32.cc	5447 const uint32_t src1[4] = {0x33333333, 0x44444444, 0x11111111, 0x22222222}; local 5453 __ Mov(r11, reinterpret_cast<uintptr_t>(src1 + 3)); 5474 ASSERT_EQUAL_32(reinterpret_cast<uintptr_t>(src1 + 1), r11);
/external/vboot_reference/tests/
H A D	stateful_util_tests.c	150 char* src1 = "Doogie"; local 159 TEST_PTR_EQ(src1, StatefulMemcpy_r(&s, src1, 6), 183 TEST_PTR_EQ(src1, StatefulMemcpy_r(&s, src1, 0), 191 TEST_PTR_EQ(NULL, StatefulMemcpy_r(&s, src1, 1), 223 char* src1 = "ThisIsATest"; local 230 StatefulInit(&s, src1, 12); 233 TEST_PTR_EQ(src1 + 6, s.remaining_buf, "StatefulMemcpy(6) buf");
/external/vboot_reference/firmware/lib/include/
H A D	utility.h	50 * Compare [n] bytes in [src1] and [src2]. 53 * [n] bytes of [src1] is found, respectively, to be less than, to match, or be 55 int Memcmp(const void *src1, const void *src2, size_t n);

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Indexes created Sun Aug 12 02:23:12 CEST 2018