/drivers/gpu/drm/radeon/ |
H A D | r600_hdmi.c | 243 unsigned long div, mul; local 250 div = gcd(n, cts); 252 n /= div; 253 cts /= div;
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/drivers/gpu/drm/tilcdc/ |
H A D | tilcdc_crtc.c | 541 unsigned int lcd_clk, div; local 558 div = lcd_clk / (crtc->mode.clock * 1000); 560 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 564 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
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/drivers/i2c/busses/ |
H A D | i2c-rk3x.c | 434 unsigned int div; local 440 div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1; 442 i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
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/drivers/media/pci/pluto2/ |
H A D | pluto2.c | 455 u32 div; local 461 //div = divide(p->frequency + 36166667, 166667); 462 div = divide(p->frequency * 3, 500000) + 217; 463 buf[0] = (div >> 8) & 0x7f; 464 buf[1] = (div >> 0) & 0xff;
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/drivers/media/tuners/ |
H A D | e4000_priv.h | 52 u8 div; member in struct:e4000_pll
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H A D | fc2580_priv.h | 53 u8 div; member in struct:fc2580_pll
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/drivers/tty/serial/ |
H A D | ar933x_uart.c | 187 u32 div; local 189 div = (2 << 16) * (scale + 1); 192 t += (div / 2); 193 do_div(t, div);
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H A D | sc16is7xx.c | 428 unsigned long clk = port->uartclk, div = clk / 16 / baud; local 430 if (div > 0xffff) { 432 div /= 4; 460 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 461 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 467 return DIV_ROUND_CLOSEST(clk / 16, div); 900 /* Enable write access to enhanced features and internal clock div */
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H A D | samsung.c | 658 unsigned long div = rate / req_baud; local 668 quot = div / 16; 669 baud = rate / div; 762 unsigned int div = ourport->baudclk_rate / baud; local 765 udivslot = (div & 15); 768 udivslot = udivslot_table[div & 15]; 769 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
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/drivers/video/fbdev/omap/ |
H A D | omapfb.h | 138 int hs_pol_inv, int vs_pol_inv, int div);
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/drivers/video/fbdev/ |
H A D | pxa168fb.h | 174 #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */ 335 #define CLK_INT_DIV(div) (div)
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H A D | nuc900fb.c | 68 * calculate divider for lcd div 74 unsigned long long div; local 77 /* div = (clk * pixclk)/10^12 */ 78 div = (unsigned long long)clk * pixclk; 79 div >>= 12; 80 do_div(div, 625 * 625UL * 625); 82 dev_dbg(fbi->dev, "pixclk %ld, divisor is %lld\n", pixclk, div); 84 return div;
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H A D | s3c2410fb.c | 101 unsigned long long div; local 108 div = (unsigned long long)clk * pixclk; 109 div >>= 12; /* div / 2^12 */ 110 do_div(div, 625 * 625UL * 625); /* div / 5^12 */ 112 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div); 113 return div;
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H A D | cirrusfb.c | 408 static void bestclock(long freq, int *nom, int *den, int *div); 632 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div) argument 640 if (div) { 642 (div == 2) ? "MCLK/2" : "MCLK"); 645 if (div == 2) 669 int nom, den, div; local 845 bestclock(freq, &nom, &den, &div); 847 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n", 848 freq, nom, den, div); 886 if (div ! 2739 bestclock(long freq, int *nom, int *den, int *div) argument [all...] |
H A D | mx3fb.c | 521 uint32_t div; local 572 div = clk_get_rate(ipu_clk) * 16 / pixel_clk; 575 div = 0; 578 if (div < 0x40) { /* Divider less than 4 */ 581 div = 0x40; 585 pixel_clk, div >> 4, (div & 7) * 125); 594 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
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/drivers/net/wireless/ath/ath9k/ |
H A D | ar9003_phy.c | 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; local 81 div = 75; 83 div = 120; 85 channelSel = (freq * 4) / div; 86 chan_frac = (((freq * 4) % div) * 0x20000) / div; 108 div = 75; 110 div = 120; 112 channelSel = (freq * 4) / div; 113 chan_frac = (((freq * 4) % div) * [all...] |
/drivers/clk/samsung/ |
H A D | clk.h | 88 * @div: fixed division factor. 96 unsigned long div; member in struct:samsung_fixed_factor_clock 106 .div = d, \ 167 * struct samsung_div_clock: information about div clock 169 * @name: name of this div clock. 172 * @offset: offset of the register for configuring the div. 173 * @shift: starting bit location of the div control bit-field in @reg. 174 * @div_flags: flags for div-type clock.
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/drivers/hwmon/ |
H A D | s3c-hwmon.c | 179 ret = DIV_ROUND_CLOSEST(ret, cfg->div); 329 if (cfg->div == 0) {
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H A D | asb100.c | 126 static u8 FAN_TO_REG(long rpm, int div) argument 133 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 136 static int FAN_FROM_REG(u8 val, int div) argument 138 return val == 0 ? -1 : val == 255 ? 0 : 1350000 / (val * div);
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H A D | gl520sm.c | 351 #define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : (480000 / ((val) << (div)))) 352 #define FAN_TO_REG(val, div) ((val) <= 0 ? 0 : \ 353 clamp_val((480000 + ((val) << ((div)-1))) / ((val) << (div)), 1, 255))
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/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/ |
H A D | kernel.fuc | 268 div $r12 $r12 1000 275 div $r14 $r14 1000 323 div $r14 $r14 $r13
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/drivers/spi/ |
H A D | spi-bfin-sport.c | 130 int div = (sclk / (2 * speed_hz)) - 1; local 132 if (div < 0) 133 div = 0; 135 clk = sclk / (2 * (div + 1)); 138 div++; 140 return div;
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/drivers/clk/tegra/ |
H A D | clk-tegra114.c | 677 { .val = 0, .div = 1 }, 678 { .val = 1, .div = 2 }, 679 { .val = 2, .div = 3 }, 680 { .val = 3, .div = 4 }, 681 { .val = 4, .div = 5 }, 682 { .val = 5, .div = 6 }, 683 { .val = 0, .div = 0 },
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H A D | clk-tegra124.c | 472 { .val = 0, .div = 1 }, 473 { .val = 1, .div = 2 }, 474 { .val = 2, .div = 3 }, 475 { .val = 3, .div = 4 }, 476 { .val = 4, .div = 5 }, 477 { .val = 5, .div = 6 }, 478 { .val = 0, .div = 0 },
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/drivers/pinctrl/ |
H A D | pinctrl-at91.c | 162 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 163 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div); 479 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) argument 481 *div = __raw_readl(pio + PIO_SCDR); 488 bool is_on, u32 div) 492 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 842 int div; local 857 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) 858 *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT); 487 at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, bool is_on, u32 div) argument
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