Searched defs:pl (Results 1 - 25 of 38) sorted by last modified time

12

/drivers/video/fbdev/
H A Damifb.c2055 u_long pl, ps, pt; local
2060 ps = pl = ZTWO_PADDR(dummysprite);
2070 pl = ZTWO_PADDR(lofsprite);
2081 pt = pl; pl = ps; ps = pt;
2091 copl[cop_spr0ptrh].w[1] = highw(pl);
2092 copl[cop_spr0ptrl].w[1] = loww(pl);
/drivers/s390/scsi/
H A Dzfcp_dbf.c42 struct zfcp_dbf_pay *pl = &dbf->pay_buf; local
46 memset(pl, 0, sizeof(*pl));
47 pl->fsf_req_id = req_id;
48 memcpy(pl->area, area, ZFCP_DBF_TAG_LEN);
53 memcpy(pl->data, data + offset, rec_length);
54 debug_event(dbf->pay, 1, pl, zfcp_dbf_plen(rec_length));
57 pl->counter++;
179 * @pl: array of all involved sbals
182 void **pl)
181 zfcp_dbf_hba_def_err(struct zfcp_adapter *adapter, u64 req_id, u16 scount, void **pl) argument
[all...]
H A Dzfcp_qdio.c92 void *pl[ZFCP_QDIO_MAX_SBALS_PER_REQ + 1]; local
97 memset(pl, 0,
108 pl[sbal_no] = qdio->res_q[sbal_idx];
110 zfcp_dbf_hba_def_err(adapter, req_id, scount, pl);
/drivers/scsi/bfa/
H A Dbfi.h169 u32 pl[BFI_LMSG_PL_WSZ]; member in struct:bfi_msg_s
178 u32 pl[BFI_MBMSG_SZ]; member in struct:bfi_mbmsg_s
/drivers/scsi/csiostor/
H A Dcsio_hw.c2237 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE); local
2260 pl &= (~SF);
2261 csio_wr_reg32(hw, pl, PL_INT_ENABLE);
/drivers/scsi/
H A Deata.c2108 unsigned long sl[n_ready], pl[n_ready], ll[n_ready]; local
2182 pl[n] = SCpnt->serial_number;
2194 sort(pl, il, n_ready, 0);
H A Du14-34f.c1585 unsigned long sl[n_ready], pl[n_ready], ll[n_ready]; local
1642 ll[n] = blk_rq_sectors(SCpnt->request); pl[n] = SCpnt->serial_number;
1650 if (overlap) sort(pl, il, n_ready, FALSE);
/drivers/scsi/libfc/
H A Dfc_rport.c1593 struct fc_els_flogi *pl; local
1601 pl = fc_frame_payload_get(fp, sizeof(*pl));
1602 if (!pl) {
1622 rdata->ids.port_name = get_unaligned_be64(&pl->fl_wwpn);
1623 rdata->ids.node_name = get_unaligned_be64(&pl->fl_wwnn);
1680 rdata->maxframe_size = fc_plogi_get_maxframe(pl, lport->mfs);
1685 fp = fc_frame_alloc(lport, sizeof(*pl));
/drivers/staging/lustre/lustre/ldlm/
H A Dldlm_pool.c181 static inline struct ldlm_namespace *ldlm_pl2ns(struct ldlm_pool *pl) argument
183 return container_of(pl, struct ldlm_namespace, ns_pool);
218 * Recalculates next grant limit on passed \a pl.
222 static void ldlm_pool_recalc_grant_plan(struct ldlm_pool *pl) argument
226 limit = ldlm_pool_get_limit(pl);
227 granted = atomic_read(&pl->pl_granted);
229 grant_step = ldlm_pool_t2gsp(pl->pl_recalc_period);
231 pl->pl_grant_plan = granted + grant_step;
233 if (pl->pl_grant_plan > limit)
234 pl
242 ldlm_pool_recalc_slv(struct ldlm_pool *pl) argument
287 ldlm_pool_recalc_stats(struct ldlm_pool *pl) argument
310 ldlm_srv_pool_push_slv(struct ldlm_pool *pl) argument
333 ldlm_srv_pool_recalc(struct ldlm_pool *pl) argument
378 ldlm_srv_pool_shrink(struct ldlm_pool *pl, int nr, gfp_t gfp_mask) argument
433 ldlm_srv_pool_setup(struct ldlm_pool *pl, int limit) argument
451 ldlm_cli_pool_pop_slv(struct ldlm_pool *pl) argument
470 ldlm_cli_pool_recalc(struct ldlm_pool *pl) argument
518 ldlm_cli_pool_shrink(struct ldlm_pool *pl, int nr, gfp_t gfp_mask) argument
562 ldlm_pool_recalc(struct ldlm_pool *pl) argument
603 ldlm_pool_shrink(struct ldlm_pool *pl, int nr, gfp_t gfp_mask) argument
631 ldlm_pool_setup(struct ldlm_pool *pl, int limit) argument
644 struct ldlm_pool *pl = m->private; local
683 struct ldlm_pool *pl = m->private; local
722 ldlm_pool_proc_init(struct ldlm_pool *pl) argument
816 ldlm_pool_proc_fini(struct ldlm_pool *pl) argument
828 ldlm_pool_proc_init(struct ldlm_pool *pl) argument
833 ldlm_pool_proc_fini(struct ldlm_pool *pl) argument
836 ldlm_pool_init(struct ldlm_pool *pl, struct ldlm_namespace *ns, int idx, ldlm_side_t client) argument
875 ldlm_pool_fini(struct ldlm_pool *pl) argument
891 ldlm_pool_add(struct ldlm_pool *pl, struct ldlm_lock *lock) argument
919 ldlm_pool_del(struct ldlm_pool *pl, struct ldlm_lock *lock) argument
943 ldlm_pool_get_slv(struct ldlm_pool *pl) argument
958 ldlm_pool_set_slv(struct ldlm_pool *pl, __u64 slv) argument
971 ldlm_pool_get_clv(struct ldlm_pool *pl) argument
986 ldlm_pool_set_clv(struct ldlm_pool *pl, __u64 clv) argument
997 ldlm_pool_get_limit(struct ldlm_pool *pl) argument
1006 ldlm_pool_set_limit(struct ldlm_pool *pl, __u32 limit) argument
1015 ldlm_pool_get_lvf(struct ldlm_pool *pl) argument
1021 ldlm_pool_granted(struct ldlm_pool *pl) argument
[all...]
H A Dldlm_request.c1453 struct ldlm_pool *pl = &ns->ns_pool; local
1462 slv = ldlm_pool_get_slv(pl);
1463 lvf = ldlm_pool_get_lvf(pl);
1469 ldlm_pool_set_clv(pl, lv);
/drivers/target/iscsi/
H A Discsi_target_parameters.c229 struct iscsi_param_list *pl; local
231 pl = kzalloc(sizeof(struct iscsi_param_list), GFP_KERNEL);
232 if (!pl) {
237 INIT_LIST_HEAD(&pl->param_list);
238 INIT_LIST_HEAD(&pl->extra_response_list);
251 param = iscsi_set_default_param(pl, AUTHMETHOD, INITIAL_AUTHMETHOD,
257 param = iscsi_set_default_param(pl, HEADERDIGEST, INITIAL_HEADERDIGEST,
263 param = iscsi_set_default_param(pl, DATADIGEST, INITIAL_DATADIGEST,
269 param = iscsi_set_default_param(pl, MAXCONNECTIONS,
276 param = iscsi_set_default_param(pl, SENDTARGET
[all...]
/drivers/net/ethernet/brocade/bna/
H A Dbfi.h97 u32 pl[BFI_MBMSG_SZ]; member in struct:bfi_mbmsg
/drivers/gpu/drm/mgag200/
H A Dmgag200_ttm.c138 mgag200_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) argument
146 *pl = mgabo->placement;
/drivers/gpu/drm/nouveau/core/subdev/clock/
H A Dgk20a.c122 u32 m, n, pl; member in struct:gk20a_clock_priv
135 priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
145 divider = priv->m * pl_to_div[priv->pl];
162 u32 pl; local
188 for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) {
189 if (pl_to_div[pl] >= low_pl) {
190 low_pl = pl;
194 for (pl
[all...]
/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c244 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) argument
249 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
251 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
253 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
293 struct ttm_placement *pl = &nvbo->placement; local
297 pl->placement = nvbo->placements;
298 set_placement_list(nvbo->placements, &pl->num_placement,
301 pl->busy_placement = nvbo->busy_placements;
302 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
555 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) argument
[all...]
/drivers/gpu/drm/radeon/
H A Dbtc_dpm.c1271 struct rv7xx_pl *pl)
1274 if ((pl->mclk == 0) || (pl->sclk == 0))
1277 if (pl->mclk == pl->sclk)
1280 if (pl->mclk > pl->sclk) {
1281 if (((pl->mclk + (pl->sclk - 1)) / pl
1269 btc_adjust_clock_combinations(struct radeon_device *rdev, const struct radeon_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) argument
2737 struct rv7xx_pl *pl; local
[all...]
H A Dci_dpm.c4874 struct ci_pl *pl = &ps->performance_levels[index]; local
4878 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4879 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4880 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4881 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4883 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4887 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4892 pi->acpi_pcie_gen = pl->pcie_gen;
4897 pi->ulv.pl = *pl;
5286 struct ci_pl *pl; local
[all...]
H A Dci_dpm.h92 struct ci_pl pl; member in struct:ci_ulv_parm
H A Dcypress_dpm.c676 struct rv7xx_pl *pl,
686 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
687 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
688 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
691 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
697 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
707 if (pl->mclk > pi->mclk_edc_enable_threshold)
710 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
713 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
716 if (cypress_get_mclk_frequency_ratio(rdev, pl
675 cypress_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) argument
827 cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_Evergreen_MCRegisterSet *mc_reg_table_data) argument
[all...]
H A Dcypress_dpm.h44 struct rv7xx_pl *pl; member in struct:evergreen_ulv_param
114 struct rv7xx_pl *pl,
H A Dkv_dpm.c2600 struct kv_pl *pl = &ps->levels[index]; local
2605 pl->sclk = sclk;
2606 pl->vddc_index = clock_info->sumo.vddcIndex;
2611 pl->ds_divider_index = 5;
2612 pl->ss_divider_index = 5;
2820 struct kv_pl *pl = &ps->levels[i]; local
2822 i, pl->sclk,
2823 kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
H A Dni_dpm.c1614 struct rv7xx_pl *pl,
1621 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1625 pl->sclk,
1626 pl->mclk);
2310 struct rv7xx_pl *pl,
2322 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2324 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2330 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2337 if (pl->mclk > pi->mclk_edc_enable_threshold)
2339 if (pl
1613 ni_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs) argument
2309 ni_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
2957 ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_NIslands_MCRegisterSet *mc_reg_table_data) argument
3925 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
4281 struct rv7xx_pl *pl; local
4305 struct rv7xx_pl *pl; local
[all...]
H A Drv6xx_dpm.c1824 struct rv6xx_pl *pl; local
1828 pl = &ps->low;
1831 pl = &ps->medium;
1835 pl = &ps->high;
1844 pl->mclk = mclk;
1845 pl->sclk = sclk;
1846 pl->vddc = le16_to_cpu(clock_info->r600.usVDDC);
1847 pl->flags = le32_to_cpu(clock_info->r600.ulFlags);
1850 if (pl->vddc == 0xff01) {
1852 pl
2011 struct rv6xx_pl *pl; local
2033 struct rv6xx_pl *pl; local
[all...]
H A Drv770_dpm.c228 struct rv7xx_pl *pl)
230 return (pl->flags & ATOM_PPLIB_R600_FLAGS_LOWPOWER) ?
613 struct rv7xx_pl *pl,
621 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
622 level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
623 level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
627 ret = rv740_populate_sclk_value(rdev, pl->sclk,
630 ret = rv730_populate_sclk_value(rdev, pl->sclk,
633 ret = rv770_populate_sclk_value(rdev, pl->sclk,
640 if (pl
227 rv770_get_seq_value(struct radeon_device *rdev, struct rv7xx_pl *pl) argument
612 rv770_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, RV770_SMC_HW_PERFORMANCE_LEVEL *level, u8 watermark_level) argument
2178 struct rv7xx_pl *pl; local
2432 struct rv7xx_pl *pl; local
2466 struct rv7xx_pl *pl; local
[all...]
H A Dsi_dpm.c1753 struct rv7xx_pl *pl,
4173 struct rv7xx_pl *pl,
4181 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4184 pl->sclk,
4185 pl->mclk);
4518 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4547 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4638 if (ulv->supported && ulv->pl.vddc) {
4857 struct rv7xx_pl *pl,
4872 level->gen2PCIE = (u8)pl
4172 si_populate_memory_timing_parameters(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) argument
4856 si_convert_power_level_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) argument
5496 si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) argument
6226 struct rv7xx_pl *pl = &ps->performance_levels[index]; local
6551 struct rv7xx_pl *pl; local
[all...]

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