/drivers/media/pci/cx23885/ |
H A D | cx23885-ioctl.c | 42 struct v4l2_dbg_register *reg) 49 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) 52 if (mc417_register_read(dev, (u16) reg->reg, &value)) 55 reg->size = 4; 56 reg->val = value; 61 struct v4l2_dbg_register *reg) 41 cx23417_g_register(struct cx23885_dev *dev, struct v4l2_dbg_register *reg) argument 60 cx23885_g_register(struct file *file, void *fh, struct v4l2_dbg_register *reg) argument 78 cx23417_s_register(struct cx23885_dev *dev, const struct v4l2_dbg_register *reg) argument 92 cx23885_s_register(struct file *file, void *fh, const struct v4l2_dbg_register *reg) argument [all...] |
H A D | cx23885-video.h | 19 int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data); 20 u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg);
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/drivers/mfd/ |
H A D | rtsx_pcr.h | 50 #define rtsx_vendor_setting_valid(reg) (!((reg) & 0x1000000)) 51 #define rts5209_vendor_setting1_valid(reg) (!((reg) & 0x80)) 52 #define rts5209_vendor_setting2_valid(reg) ((reg) & 0x80) 54 #define rtsx_reg_to_aspm(reg) (((reg) >> 28) & 0x03) 55 #define rtsx_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 2 [all...] |
H A D | tps65912-irq.c | 45 u8 reg; local 49 tps65912->read(tps65912, TPS65912_INT_STS, 1, ®); 50 irq_sts = reg; 51 tps65912->read(tps65912, TPS65912_INT_STS2, 1, ®); 52 irq_sts |= reg << 8; 53 tps65912->read(tps65912, TPS65912_INT_STS3, 1, ®); 54 irq_sts |= reg << 16; 55 tps65912->read(tps65912, TPS65912_INT_STS4, 1, ®); 56 irq_sts |= reg << 24; 58 tps65912->read(tps65912, TPS65912_INT_MSK, 1, ®); 109 u8 reg; local 161 u8 reg; local [all...] |
/drivers/scsi/ |
H A D | dtc.h | 59 #define DTC_address(reg) (base + DTC_5380_OFFSET + reg) 61 #define dbNCR5380_read(reg) \ 62 (rval=readb(DTC_address(reg)), \ 64 , (reg), DTC_address(reg), rval)), rval ) ) 66 #define dbNCR5380_write(reg, value) do { \ 68 (value), (reg), DTC_address(reg)); \ 69 writeb(value, DTC_address(reg));} whil [all...] |
/drivers/media/platform/s5p-jpeg/ |
H A D | jpeg-hw-s5p.c | 22 unsigned long reg; local 25 reg = readl(regs + S5P_JPG_SW_RESET); 27 while (reg != 0) { 29 reg = readl(regs + S5P_JPG_SW_RESET); 40 unsigned long reg, m; local 48 reg = readl(regs + S5P_JPGCMOD); 49 reg &= ~S5P_MOD_SEL_MASK; 50 reg |= m; 51 writel(reg, regs + S5P_JPGCMOD); 56 unsigned long reg; local 68 unsigned long reg, m; local 83 unsigned long reg, m; local 103 unsigned long reg; local 118 unsigned long reg; local 128 unsigned long reg; local 139 unsigned long reg; local 150 unsigned long reg; local 165 unsigned long reg; local 180 unsigned long reg; local 191 unsigned long reg; local 202 unsigned long reg; local 213 unsigned long reg; local 224 unsigned long reg; local 239 unsigned long reg; local 248 unsigned long reg; local 265 unsigned long reg; local 274 unsigned long reg, f; local 300 unsigned long reg; local [all...] |
H A D | jpeg-hw-exynos3250.c | 23 u32 reg = 0; local 28 while (reg != 0 && --count > 0) { 31 reg = readl(regs + EXYNOS3250_SW_RESET); 34 reg = 0; 37 while (reg != 1 && --count > 0) { 41 reg = readl(regs + EXYNOS3250_JPGDRI); 65 u32 reg; local 67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; 69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); 74 u32 reg; local 125 u32 reg; local 137 u32 reg, m; local 151 u32 reg, m = 0; local 179 u32 reg; local 187 unsigned long reg; local 198 unsigned long reg; local 210 unsigned long reg; local 222 u32 reg; local 230 u32 reg; local 250 u32 reg; local 265 u32 reg; local 273 u32 reg; local 369 u32 reg; local [all...] |
H A D | jpeg-hw-exynos4.c | 21 unsigned int reg; local 23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); 33 unsigned int reg; local 35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | 42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | 50 unsigned int reg; local 52 reg 123 unsigned int reg; local 177 unsigned int reg; local 191 unsigned int reg; local 226 unsigned int reg; local [all...] |
/drivers/gpu/drm/exynos/ |
H A D | exynos_dp_reg.c | 29 u32 reg; local 32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 33 reg |= HDCP_VIDEO_MUTE; 34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 37 reg &= ~HDCP_VIDEO_MUTE; 38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 44 u32 reg; local 46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); 47 reg 53 u32 reg; local 67 u32 reg; local 109 u32 reg; local 159 u32 reg; local 180 u32 reg; local 191 u32 reg; local 208 u32 reg; local 293 u32 reg; local 328 u32 reg; local 342 u32 reg; local 356 u32 reg; local 383 u32 reg; local 393 u32 reg; local 418 u32 reg; local 434 u32 reg; local 443 int reg; local 489 u32 reg; local 534 u32 reg; local 580 u32 reg; local 644 u32 reg; local 709 u32 reg; local 743 u32 reg; local 788 u32 reg; local 857 u32 reg; local 866 u32 reg; local 874 u32 reg; local 882 u32 reg; local 890 u32 reg; local 906 u32 reg; local 938 u32 reg; local 948 u32 reg; local 958 u32 reg; local 968 u32 reg; local 979 u32 reg; local 988 u32 reg; local 997 u32 reg; local 1006 u32 reg; local 1014 u32 reg; local 1022 u32 reg; local 1030 u32 reg; local 1038 u32 reg; local 1046 u32 reg; local 1061 u32 reg; local 1081 u32 reg; local 1101 u32 reg; local 1132 u32 reg; local 1164 u32 reg; local 1179 u32 reg; local 1196 u32 reg; local 1205 u32 reg; local 1221 u32 reg; local 1249 u32 reg; local 1258 u32 reg; local [all...] |
/drivers/net/ethernet/intel/e1000/ |
H A D | e1000_osdep.h | 54 #define er32(reg) \ 56 ? E1000_##reg : E1000_82542_##reg))) 58 #define ew32(reg, value) \ 60 ? E1000_##reg : E1000_82542_##reg)))) 62 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 64 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 67 #define E1000_READ_REG_ARRAY(a, reg, offse [all...] |
/drivers/media/i2c/smiapp/ |
H A D | smiapp-regs.h | 31 #define SMIAPP_REG_ADDR(reg) ((u16)reg) 32 #define SMIAPP_REG_WIDTH(reg) ((u8)(reg >> 16)) 33 #define SMIAPP_REG_FLAGS(reg) ((u8)(reg >> 24)) 44 int smiapp_read_no_quirk(struct smiapp_sensor *sensor, u32 reg, u32 *val); 45 int smiapp_read(struct smiapp_sensor *sensor, u32 reg, u32 *val); 46 int smiapp_read_8only(struct smiapp_sensor *sensor, u32 reg, u32 *val); 47 int smiapp_write_no_quirk(struct smiapp_sensor *sensor, u32 reg, u3 [all...] |
/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_dcb_82598.c | 46 u32 reg = 0; local 51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; 52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); 54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); 56 reg &= ~IXGBE_RMCS_ARBDIS; 58 reg |= IXGBE_RMCS_RRM; 60 reg |= IXGBE_RMCS_DFP; 62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); 69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); 72 reg | 104 u32 reg, max_credits; local 150 u32 reg; local 193 u32 fcrtl, reg; local 246 u32 reg = 0; local [all...] |
H A D | ixgbe_dcb_82599.c | 51 u32 reg = 0; local 60 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; 61 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); 64 reg = 0; 66 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); 67 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); 73 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); 75 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; 78 reg |= IXGBE_RTRPT4C_LSP; 80 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); 109 u32 reg, max_credits; local 161 u32 reg; local 215 u32 i, j, fcrtl, reg; local 294 u32 reg = 0; local [all...] |
/drivers/net/ethernet/sfc/ |
H A D | io.h | 83 unsigned int reg) 85 __raw_writeq((__force u64)value, efx->membase + reg); 87 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) argument 89 return (__force __le64)__raw_readq(efx->membase + reg); 94 unsigned int reg) 96 __raw_writel((__force u32)value, efx->membase + reg); 98 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) argument 100 return (__force __le32)__raw_readl(efx->membase + reg); 105 unsigned int reg) 110 "writing register %x with " EFX_OWORD_FMT "\n", reg, 82 _efx_writeq(struct efx_nic *efx, __le64 value, unsigned int reg) argument 93 _efx_writed(struct efx_nic *efx, __le32 value, unsigned int reg) argument 104 efx_writeo(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg) argument 150 efx_writed(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg) argument 162 efx_reado(struct efx_nic *efx, efx_oword_t *value, unsigned int reg) argument 201 efx_readd(struct efx_nic *efx, efx_dword_t *value, unsigned int reg) argument 212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, unsigned int reg, unsigned int index) argument 219 efx_reado_table(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int index) argument 233 _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, unsigned int reg, unsigned int page) argument 262 _efx_writed_page(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) argument 282 _efx_writed_page_locked(struct efx_nic *efx, const efx_dword_t *value, unsigned int reg, unsigned int page) argument [all...] |
/drivers/video/fbdev/exynos/ |
H A D | exynos_mipi_dsi_lowlevel.c | 34 unsigned int reg; local 36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 38 reg |= DSIM_FUNCRST; 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 45 unsigned int reg; local 47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); 49 reg |= DSIM_SWRST; 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); 56 unsigned int reg; local 58 reg 73 unsigned int reg; local 83 unsigned int reg = 0; local 96 unsigned int reg; local 119 unsigned int reg; local 134 unsigned int reg; local 151 unsigned int reg; local 167 unsigned int reg; local 180 unsigned int reg; local 194 unsigned int reg; local 232 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & local 256 unsigned int reg; local 283 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR); local 298 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & local 309 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL); local 319 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & local 331 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & local 348 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & local 359 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & local 370 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & local 381 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & local 394 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL); local 408 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & local 418 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); local 437 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & local 448 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & local 459 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & local 470 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); local 483 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); local 496 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & local 507 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); local 518 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & local 528 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & local 544 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); local 554 unsigned int reg = 0; local 566 unsigned int reg; local 581 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0); local 589 unsigned int reg = (data0 << 8) | (di << 0); local 601 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); local 608 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); local [all...] |
/drivers/net/phy/ |
H A D | bcm63xx.c | 25 int reg, err; local 27 reg = phy_read(phydev, MII_BCM63XX_IR); 28 if (reg < 0) 29 return reg; 32 reg |= MII_BCM63XX_IR_GMASK; 33 err = phy_write(phydev, MII_BCM63XX_IR, reg); 38 reg = ~(MII_BCM63XX_IR_DUPLEX | 42 return phy_write(phydev, MII_BCM63XX_IR, reg); 47 int reg; local 50 reg 59 int reg, err; local [all...] |
/drivers/video/fbdev/riva/ |
H A D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ 45 nvCONTROL[(NV_##device##_##reg)/4] 47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) 48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) 49 #define DEVICE_PRINT(device,reg) \ 50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 56 #define PDAC_Write(reg,valu [all...] |
/drivers/clk/ |
H A D | clk-highbank.c | 50 void __iomem *reg; member in struct:hb_clk 58 u32 reg; local 60 reg = readl(hbclk->reg); 61 reg &= ~HB_PLL_RESET; 62 writel(reg, hbclk->reg); 64 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) 66 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) 75 u32 reg; local 85 u32 reg; local 97 u32 reg; local 108 unsigned long divf, divq, vco_freq, reg; local 161 u32 reg; local 276 u32 reg; local [all...] |
/drivers/scsi/qla2xxx/ |
H A D | qla_dbg.c | 121 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 128 WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); 137 WRT_REG_WORD(®->mailbox1, LSW(addr)); 138 WRT_REG_WORD(®->mailbox8, MSW(addr)); 140 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); 141 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); 142 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); 143 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); 145 WRT_REG_WORD(®->mailbox4, MSW(dwords)); 146 WRT_REG_WORD(® 201 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 294 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, uint32_t count, uint32_t *buf) argument 308 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) argument 324 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 381 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local 459 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, uint16_t *buf) argument 630 device_reg_t __iomem *reg; local 689 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local 852 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local 1044 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 1299 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 1618 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 1939 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local 2647 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local [all...] |
/drivers/regulator/ |
H A D | vexpress.c | 34 struct vexpress_regulator *reg = rdev_get_drvdata(regdev); local 36 int err = regmap_read(reg->regmap, 0, &uV); 44 struct vexpress_regulator *reg = rdev_get_drvdata(regdev); local 46 return regmap_write(reg->regmap, 0, min_uV); 60 struct vexpress_regulator *reg; local 64 reg = devm_kzalloc(&pdev->dev, sizeof(*reg), GFP_KERNEL); 65 if (!reg) 68 reg->regmap = devm_regmap_init_vexpress_config(&pdev->dev); 69 if (IS_ERR(reg [all...] |
/drivers/isdn/hisax/ |
H A D | amd7930_fn.h | 19 #define rByteAMD(cs, reg) cs->readisac(cs, reg) 20 #define wByteAMD(cs, reg, val) cs->writeisac(cs, reg, val) 21 #define rWordAMD(cs, reg) ReadWordAmd7930(cs, reg) 22 #define wWordAMD(cs, reg, val) WriteWordAmd7930(cs, reg, val)
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/drivers/net/ethernet/intel/ixgb/ |
H A D | ixgb_osdep.h | 48 #define IXGB_WRITE_REG(a, reg, value) ( \ 49 writel((value), ((a)->hw_addr + IXGB_##reg))) 51 #define IXGB_READ_REG(a, reg) ( \ 52 readl((a)->hw_addr + IXGB_##reg)) 54 #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \ 55 writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2)))) 57 #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \ 58 readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
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/drivers/tty/serial/ |
H A D | samsung.h | 73 #define portaddr(port, reg) ((port)->membase + (reg)) 74 #define portaddrl(port, reg) \ 75 ((unsigned long *)(unsigned long)((port)->membase + (reg))) 77 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg))) 78 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) 80 #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg)) [all...] |
/drivers/scsi/aic94xx/ |
H A D | aic94xx_reg.c | 128 u32 reg) \ 131 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ 137 u32 reg, type val) \ 140 u32 map_offs = (reg - io_handle->ww##_base) + asd_mem_offs_##ww();\ 186 * @reg: register desired to be within range of the new window 188 static void asd_move_swb(struct asd_ha_struct *asd_ha, u32 reg) argument 190 u32 base = reg & ~(MBAR0_SWB_SIZE-1); 195 static void __asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val) argument 198 BUG_ON(reg >= 0xC0000000 || reg < ALL_BASE_ADD 243 __asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg) argument [all...] |
/drivers/net/wireless/ath/ |
H A D | regd.c | 26 static int __ath_regd_init(struct ath_regulatory *reg); 117 static bool dynamic_country_user_possible(struct ath_regulatory *reg) argument 122 switch (reg->country_code) { 189 static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg) argument 193 if (!dynamic_country_user_possible(reg)) 205 static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg) argument 207 return reg->current_rd & ~WORLDWIDE_ROAMING_FLAG; 210 bool ath_is_world_regd(struct ath_regulatory *reg) argument 212 return is_wwr_sku(ath_regd_get_eepromRD(reg)); 223 ieee80211_regdomain *ath_world_regdomain(struct ath_regulatory *reg) argument 304 __ath_reg_apply_beaconing_flags(struct wiphy *wiphy, struct ath_regulatory *reg, enum nl80211_reg_initiator initiator, struct ieee80211_channel *ch) argument 335 ath_reg_apply_beaconing_flags(struct wiphy *wiphy, struct ath_regulatory *reg, enum nl80211_reg_initiator initiator) argument 371 ath_reg_apply_ir_flags(struct wiphy *wiphy, struct ath_regulatory *reg, enum nl80211_reg_initiator initiator) argument 430 ath_reg_apply_world_flags(struct wiphy *wiphy, enum nl80211_reg_initiator initiator, struct ath_regulatory *reg) argument 464 __ath_reg_dyn_country(struct wiphy *wiphy, struct ath_regulatory *reg, struct regulatory_request *request) argument 488 ath_reg_dyn_country(struct wiphy *wiphy, struct ath_regulatory *reg, struct regulatory_request *request) argument 501 ath_reg_notifier_apply(struct wiphy *wiphy, struct regulatory_request *request, struct ath_regulatory *reg) argument 544 ath_regd_is_eeprom_valid(struct ath_regulatory *reg) argument 628 ath_regd_init_wiphy(struct ath_regulatory *reg, struct wiphy *wiphy, void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)) argument 668 ath_regd_sanitize(struct ath_regulatory *reg) argument 676 __ath_regd_init(struct ath_regulatory *reg) argument 751 ath_regd_init(struct ath_regulatory *reg, struct wiphy *wiphy, void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)) argument 774 ath_regd_get_band_ctl(struct ath_regulatory *reg, enum ieee80211_band band) argument [all...] |