Searched refs:VT (Results 1 - 25 of 112) sorted by last modified time

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/external/webkit/Source/WebKit/android/content/
H A Daddress_detector.cpp724 VT = 54, // VT Vermont enumerator in enum:USState
738 VT, VT, VT, VT, VT, MA, VT, VT, VT, V
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/external/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp87 Record *VT = VTs->getElementAsRecord(i); local
89 O << "LocVT == " << getEnumName(getValueType(VT));
H A DCodeGenDAGPatterns.cpp32 static inline bool isInteger(MVT::SimpleValueType VT) { argument
33 return EVT(VT).isInteger();
35 static inline bool isFloatingPoint(MVT::SimpleValueType VT) { argument
36 return EVT(VT).isFloatingPoint();
38 static inline bool isVector(MVT::SimpleValueType VT) { argument
39 return EVT(VT).isVector();
41 static inline bool isScalar(MVT::SimpleValueType VT) { argument
42 return !EVT(VT).isVector();
45 EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) { argument
46 if (VT
875 MVT::SimpleValueType VT = local
1556 MVT::SimpleValueType VT = local
1587 MVT::SimpleValueType VT; local
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H A DCodeGenDAGPatterns.h61 TypeSet(MVT::SimpleValueType VT, TreePattern &TP);
127 /// EnforceSmallerThan - 'this' must be a smaller VT than Other. Update
132 /// whose element is VT.
133 bool EnforceVectorEltTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
136 /// be a vector type VT.
137 bool EnforceVectorSubVectorTypeIs(EEVT::TypeSet &VT, TreePattern &TP);
169 MVT::SimpleValueType VT;
453 /// UpdateNodeType - Set the node type of N to VT if VT contains
H A DCodeGenTarget.cpp454 MVT::SimpleValueType VT; local
459 VT = OverloadedVTs[MatchTy];
465 VT == MVT::iAny || VT == MVT::vAny) &&
468 VT = getValueType(TyEl->getValueAsDef("VT"));
470 if (EVT(VT).isOverloaded()) {
471 OverloadedVTs.push_back(VT);
476 if (VT == MVT::isVoid)
479 IS.RetVTs.push_back(VT);
488 MVT::SimpleValueType VT; local
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H A DCodeGenTarget.h139 bool isLegalValueType(MVT::SimpleValueType VT) const {
142 if (LegalVTs[i] == VT) return true;
H A DDAGISelMatcher.cpp210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n'; local
215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n'; local
224 OS << " VT=" << VT << '\n'; local
293 return HashString(Val) ^ VT;
H A DDAGISelMatcher.h772 MVT::SimpleValueType VT; member in class:llvm::EmitIntegerMatcher
775 : Matcher(EmitInteger), Val(val), VT(vt) {}
778 MVT::SimpleValueType getVT() const { return VT; }
788 cast<EmitIntegerMatcher>(M)->VT == VT;
790 virtual unsigned getHashImpl() const { return (Val << 4) | VT; }
797 MVT::SimpleValueType VT; member in class:llvm::EmitStringIntegerMatcher
800 : Matcher(EmitStringInteger), Val(val), VT(vt) {}
803 MVT::SimpleValueType getVT() const { return VT; }
813 cast<EmitStringIntegerMatcher>(M)->VT
823 MVT::SimpleValueType VT; member in class:llvm::EmitRegisterMatcher
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H A DDAGISelMatcherGen.cpp27 MVT::SimpleValueType VT = MVT::Other; local
38 VT = RC.getValueTypeNum(0);
43 assert(VT == RC.getValueTypeNum(0));
45 return VT;
H A DFastISelEmitter.cpp160 OS << "VT == "
175 MVT::SimpleValueType VT,
218 //if (Op->getType(0) != VT)
245 if (Op->getType(0) != VT)
495 MVT::SimpleValueType VT = RetVT;
498 VT = InstPatNode->getChild(0)->getType(0);
507 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates))
552 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck))
556 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
601 MVT::SimpleValueType VT
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H A DIntrinsicEmitter.cpp247 static void EncodeFixedValueType(MVT::SimpleValueType VT, argument
249 if (EVT(VT).isInteger()) {
250 unsigned BitWidth = EVT(VT).getSizeInBits();
261 switch (VT) {
291 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT")); local
294 switch (VT) {
328 if (EVT(VT).isVector()) {
329 EVT VVT = VT;
343 EncodeFixedValueType(VT, Si
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H A DRegisterInfoEmitter.cpp482 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { argument
483 OS << getEnumName(VT);
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp177 bool isTypeLegal(Type *Ty, MVT &VT);
178 bool isLoadTypeLegal(Type *Ty, MVT &VT);
181 bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr,
184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
187 void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3);
191 unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
192 unsigned ARMMaterializeInt(const Constant *C, EVT VT);
193 unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
194 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195 unsigned ARMMoveToIntReg(EVT VT, unsigne
488 ARMMoveToFPReg(EVT VT, unsigned SrcReg) argument
498 ARMMoveToIntReg(EVT VT, unsigned SrcReg) argument
511 ARMMaterializeFP(const ConstantFP *CFP, EVT VT) argument
555 ARMMaterializeInt(const Constant *C, EVT VT) argument
615 ARMMaterializeGV(const GlobalValue *GV, EVT VT) argument
712 EVT VT = TLI.getValueType(C->getType(), true); local
755 isTypeLegal(Type *Ty, MVT &VT) argument
767 isLoadTypeLegal(Type *Ty, MVT &VT) argument
891 ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3) argument
947 AddLoadStoreOperands(EVT VT, Address &Addr, const MachineInstrBuilder &MIB, unsigned Flags, bool useAM3) argument
996 ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment, bool isZExt, bool allocReg) argument
1114 ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) argument
1638 MVT VT; local
1698 MVT VT; local
1726 MVT VT; local
1786 EVT VT = TLI.getValueType(I->getType(), true); local
2405 MVT VT; local
2748 MVT VT; local
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H A DARMISelDAGToDAG.cpp269 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
270 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
271 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1445 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) { argument
1452 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1457 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) { argument
1463 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Op
1468 PairQRegs(EVT VT, SDValue V0, SDValue V1) argument
1479 QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1495 QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1510 QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1604 EVT VT = N->getValueType(0); local
1741 EVT VT = N->getOperand(Vec0Idx).getValueType(); local
1889 EVT VT = N->getOperand(Vec0Idx).getValueType(); local
2004 EVT VT = N->getValueType(0); local
2078 EVT VT = N->getValueType(0); local
2278 EVT VT = N->getValueType(0); local
2378 EVT VT = N->getValueType(0); local
2407 EVT VT = N->getValueType(0); local
2726 EVT VT = N->getValueType(0); local
2746 EVT VT = N->getValueType(0); local
2766 EVT VT = N->getValueType(0); local
3278 EVT VT = N->getValueType(0); local
3289 EVT VT = N->getValueType(0); local
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H A DARMISelLowering.cpp93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, argument
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custo
151 addDRTypeForNEON(MVT VT) argument
156 addQRTypeForNEON(MVT VT) argument
1058 EVT VT = N->getValueType(i); local
2881 EVT VT = Op.getValueType(); local
2902 EVT VT = Op.getValueType(); local
3137 EVT VT = Op.getValueType(); local
3156 EVT VT = Op.getValueType(); local
3177 EVT VT = Op.getValueType(); local
3210 EVT VT = Op.getValueType(); local
3236 EVT VT = Op.getValueType(); local
3318 EVT VT = Op.getValueType(); local
3338 EVT VT = Op.getValueType(); local
3395 getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
3409 EVT VT = Op.getValueType(); local
3445 EVT VT = Op.getValueType(); local
3494 EVT VT = N->getValueType(0); local
3506 EVT VT = N->getValueType(0); local
3541 EVT VT = N->getValueType(0); local
3586 EVT VT = Op.getValueType(); local
3711 isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, EVT &VT, bool is128Bits, NEONModImmType type) argument
3896 isVEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseVEXT, unsigned &Imm) argument
3935 isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) argument
3961 isVTBLMask(ArrayRef<int> M, EVT VT) argument
3968 isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
3986 isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
4001 isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
4024 isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
4048 isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
4073 isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) argument
4121 EVT VT = Op.getValueType(); local
4293 EVT VT = Op.getValueType(); local
4512 EVT VT = OpLHS.getValueType(); local
4581 EVT VT = Op.getValueType(); local
4768 EVT VT = N->getValueType(0); local
4858 EVT VT = N->getValueType(0); local
4899 EVT VT = Op.getValueType(); local
5037 EVT VT = Op.getValueType(); local
5072 EVT VT = Op.getValueType(); local
5146 EVT VT = Op.getNode()->getValueType(0); local
7071 EVT VT = N->getValueType(0); local
7119 EVT VT = N->getValueType(0); local
7476 EVT VT = N->getValueType(0); local
7576 EVT VT = N->getValueType(0); local
7619 EVT VT = N->getValueType(0); local
7806 EVT VT = N->getValueType(0); local
7917 EVT VT = StVal.getValueType(); local
8075 EVT VT = N->getValueType(0); local
8098 EVT VT = N->getValueType(0); local
8145 EVT VT = N->getValueType(0); local
8309 EVT VT = N->getValueType(0); local
8409 EVT VT = N->getValueType(0); local
8537 isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) argument
8551 isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt) argument
8592 EVT VT = N->getOperand(1).getValueType(); local
8697 EVT VT = N->getOperand(1).getValueType(); local
8730 EVT VT = N->getValueType(0); local
8786 EVT VT = N->getValueType(0); local
9079 isLegalT1AddressImmediate(int64_t V, EVT VT) argument
9106 isLegalT2AddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument
9139 isLegalAddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) argument
9213 EVT VT = getValueType(Ty, true); local
9299 getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
9358 getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) argument
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H A DARMISelLowering.h269 virtual EVT getSetCCResultType(EVT VT) const;
281 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
285 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
296 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
344 EVT VT) const;
361 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
374 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
380 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
387 findRepresentativeClass(EVT VT) const;
402 void addTypeForNEON(MVT VT, MV
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H A DARMSelectionDAGInfo.cpp52 EVT VT = MVT::i32; local
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
/external/llvm/lib/Target/CellSPU/
H A DSPUISelDAGToDAG.cpp572 \arg VT the value type for which we want a register class
574 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
575 switch( VT.SimpleTy ) {
834 EVT VT = N->getValueType(0); local
839 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
841 getRC( VT.getSimpleVT()), Chain);
851 EVT VT = N->getValueType(0); local
864 Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
H A DSPUISelLowering.cpp39 int prefslotOffset(EVT VT) { argument
41 if (VT==MVT::i1) retval=3;
42 if (VT==MVT::i8) retval=3;
43 if (VT==MVT::i16) retval=2;
135 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype; local
137 setOperationAction(ISD::LOAD, VT, Custom);
138 setOperationAction(ISD::STORE, VT, Custom);
139 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, VT, Custo
151 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype; local
371 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype; local
411 MVT::SimpleValueType VT = (MVT::SimpleValueType)i; local
772 EVT VT = Value.getValueType(); local
1096 EVT VT = Op.getValueType(); local
1659 EVT VT = Op.getValueType(); local
1967 EVT VT; local
2004 EVT VT = Op.getValueType(); local
2171 EVT VT = Op.getValueType(); local
2305 EVT VT = Op.getValueType(); local
2356 EVT VT = Op.getValueType(); local
2649 EVT VT = Op.getValueType(); local
2678 EVT VT = Op.getValueType(); local
2782 EVT VT = Op.getValueType(); local
3205 EVT VT = Op.getValueType(); local
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H A DSPUISelLowering.h109 virtual EVT getSetCCResultType(EVT VT) const;
140 EVT VT) const;
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT; local
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT; local
187 if (Fn(i, VT, V
197 AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) argument
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H A DHexagonCallingConvLower.h107 void AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn);
H A DHexagonISelLowering.cpp591 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, argument
598 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
635 EVT VT; local
640 VT = LD->getMemoryVT();
643 VT = ST->getMemoryVT();
652 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
655 int ShiftAmount = VT
962 EVT VT = Op.getValueType(); local
984 EVT VT = Op.getValueType(); local
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H A DHexagonISelLowering.h128 virtual EVT getSetCCResultType(EVT VT) const {
139 EVT VT) const;
150 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
H A DHexagonInstrInfo.cpp446 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
450 if (VT == MVT::i1) {
452 } else if (VT == MVT::i32 || VT == MVT::f32) {
454 } else if (VT == MVT::i64 || VT == MVT::f64) {
2472 isValidAutoIncImm(const EVT VT, const int Offset) const { argument
2474 if (VT == MVT::i64) {
2479 if (VT == MVT::i32) {
2484 if (VT
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