/external/llvm/lib/MC/ |
H A D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, 49 .addReg(DestReg, getDefRegState(true), SubIdx) 35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | Thumb1RegisterInfo.cpp | 68 unsigned DestReg, unsigned SubIdx, 79 .addReg(DestReg, getDefRegState(true), SubIdx) 65 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMBaseRegisterInfo.cpp | 708 unsigned DestReg, unsigned SubIdx, int Val, 718 .addReg(DestReg, getDefRegState(true), SubIdx) 705 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
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H A D | ARMISelDAGToDAG.cpp | 2064 unsigned SubIdx = ARM::dsub_0; local 2067 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
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H A D | ARMBaseInstrInfo.cpp | 744 unsigned Reg, unsigned SubIdx, unsigned State, 746 if (!SubIdx) 750 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); 751 return MIB.addReg(Reg, State, SubIdx); 1221 unsigned DestReg, unsigned SubIdx, 1228 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 743 AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) argument 1219 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 104 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 105 unsigned SubIdx = MI->getOperand(3).getImm(); local 107 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 124 MI->RemoveOperand(3); // SubIdx
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H A D | MachineCopyPropagation.cpp | 117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); local 118 if (!SubIdx) 120 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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H A D | PeepholeOptimizer.cpp | 144 unsigned SrcReg, DstReg, SubIdx; local 145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 159 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx); 166 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of 167 // SrcReg:SubIdx should be replaced. 169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 199 // Only accept uses of SrcReg:SubIdx. 200 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) 280 .addReg(DstReg, 0, SubIdx); 281 // SubIdx applie [all...] |
H A D | MachineInstr.cpp | 70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument 73 if (SubIdx && getSubReg()) 74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 76 if (SubIdx) 77 setSubReg(SubIdx); 1297 unsigned SubIdx, 1300 if (SubIdx) 1301 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1313 MO.substVirtReg(ToReg, SubIdx, RegInf [all...] |
H A D | TargetInstrInfoImpl.cpp | 225 unsigned SubIdx, 229 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); 222 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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H A D | LiveDebugVariables.cpp | 250 /// renameRegister - Update locations to rewrite OldReg as NewReg:SubIdx. 251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, 337 /// renameRegister - Replace all references to OldReg with NewReg:SubIdx. 338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx); 718 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, argument 728 Loc.substVirtReg(NewReg, SubIdx, *TRI); 734 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument 745 UV->renameRegister(OldReg, NewReg, SubIdx, TRI); 751 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument 753 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx); [all...] |
H A D | MachineVerifier.cpp | 867 unsigned SubIdx = MO->getSubReg(); local 870 if (SubIdx) { 885 if (SubIdx) { 887 TRI->getSubClassWithSubReg(RC, SubIdx); 891 << " does not support subreg index " << SubIdx << "\n"; 897 << " does not fully support subreg index " << SubIdx << "\n"; 903 if (SubIdx) { 910 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
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H A D | RegisterCoalescer.cpp | 159 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 304 "Cannot have a physical SubIdx"); 845 unsigned SubIdx) { 850 LDV->renameRegister(SrcReg, DstReg, SubIdx); 860 if (DstInt && !Reads && SubIdx) 870 if (SubIdx && MO.isDef()) 876 MO.substVirtReg(DstReg, SubIdx, *TRI); 843 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
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H A D | TwoAddressInstructionPass.cpp | 1451 unsigned SubIdx = mi->getOperand(3).getImm(); local 1454 mi->getOperand(0).setSubReg(SubIdx); 1476 unsigned DstReg, unsigned SubIdx, 1483 MO.substVirtReg(DstReg, SubIdx, TRI); 1682 unsigned SubIdx = MI->getOperand(i+1).getImm(); local 1707 MRI->getRegClass(SrcReg), SubIdx)) { 1736 .addReg(DstReg, RegState::Define, SubIdx) 1748 unsigned SubIdx = MI->getOperand(i+1).getImm(); local 1749 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI); 1475 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument
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/external/llvm/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 41 if (SubIdx) { 43 OS << ':' << TRI->getSubRegIndexName(SubIdx); 45 OS << ":sub(" << SubIdx << ')'; local
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/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 329 const char *getSubRegIndexName(unsigned SubIdx) const { 330 assert(SubIdx && "This is not a subregister index"); 331 return SubRegIndexNames[SubIdx-1]; 413 /// Reg so its sub-register of index SubIdx is Reg. 414 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument 416 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 849 unsigned SubIdx; member in class:llvm::PrintReg 852 : TRI(tri), Reg(reg), SubIdx(subidx) {}
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 302 // registers have a SubIdx sub-register. 304 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const { 305 return SubClassWithSubReg.lookup(SubIdx); 308 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, argument 310 SubClassWithSubReg[SubIdx] = SubRC; 314 // containing only SubIdx super-registers of this class. 315 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const; 318 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument 320 SuperRegClasses[SubIdx].insert(SuperRC);
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H A D | AsmMatcherEmitter.cpp | 1618 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; local 1625 int SrcOperand = findAsmOperand(Name, SubIdx); 1630 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
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H A D | CodeGenRegisters.cpp | 461 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); local 462 if (!SubIdx) 465 NewIdx->addComposite(SI->first, SubIdx); 487 // Topological signature computed from SubIdx, TopoId(SubReg). 924 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, argument 928 FindI = SuperRegClasses.find(SubIdx); 1428 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); 1429 SubIdx != EndIdx; ++SubIdx) { 1430 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; 1629 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local 1662 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1332 unsigned &SubIdx) const { 1364 SubIdx = X86::sub_8bit; 1370 SubIdx = X86::sub_16bit; 1374 SubIdx = X86::sub_32bit; 1675 unsigned DestReg, unsigned SubIdx, 1712 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1673 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
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