| /external/llvm/lib/CodeGen/ |
| H A D | TargetFrameLoweringImpl.cpp | 37 int FI, unsigned &FrameReg) const {
43 FrameReg = RI->getFrameRegister(MF);
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16RegisterInfo.cpp | 78 unsigned FrameReg; local
82 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
84 FrameReg = getFrameRegister(MF);
106 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
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| H A D | MipsSERegisterInfo.cpp | 92 unsigned FrameReg; local
96 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
98 FrameReg = getFrameRegister(MF);
129 BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg);
131 FrameReg = ATReg;
135 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.h | 53 unsigned &FrameReg) const;
56 unsigned &FrameReg, int SPAdj) const;
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| H A D | Thumb1RegisterInfo.cpp | 388 unsigned FrameReg, int &Offset,
403 if (FrameReg != ARM::SP) {
417 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
432 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
435 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
447 emitThumbRegPlusImmediate(MBB, II, dl, DestReg, FrameReg, Offset, TII,
461 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
463 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
478 MI.getOperand(FrameRegIdx+1).ChangeToRegister(FrameReg, false);
487 unsigned NumBits = (FrameReg
[all...] |
| H A D | Thumb1RegisterInfo.h | 55 unsigned FrameReg, int &Offset,
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| H A D | Thumb2InstrInfo.cpp | 389 unsigned FrameReg, int &Offset,
407 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
428 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
441 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
477 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
532 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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| H A D | ARMFrameLowering.cpp | 482 unsigned &FrameReg) const {
483 return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
488 int FI, unsigned &FrameReg,
498 FrameReg = ARM::SP;
516 FrameReg = RegInfo->getFrameRegister(MF);
521 FrameReg = RegInfo->getBaseRegister();
531 FrameReg = RegInfo->getFrameRegister(MF);
540 FrameReg = RegInfo->getFrameRegister(MF);
553 FrameReg = RegInfo->getFrameRegister(MF);
558 FrameReg
487 ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const argument
570 unsigned FrameReg; local
[all...] |
| H A D | ARMBaseRegisterInfo.cpp | 1080 unsigned FrameReg;
1082 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1089 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){
1101 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
1109 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1112 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1132 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1136 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1140 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
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| H A D | ARMBaseInstrInfo.h | 400 unsigned FrameReg, int &Offset,
404 unsigned FrameReg, int &Offset,
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| H A D | ARMBaseInstrInfo.cpp | 1764 unsigned FrameReg, int &Offset,
1780 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1793 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1871 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
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| H A D | ARMISelLowering.cpp | 3341 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) local
3343 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 189 unsigned FrameReg = getFrameRegister(MF); local
193 MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
230 .addReg(FrameReg)
236 .addReg(FrameReg)
241 .addReg(FrameReg)
251 .addReg(FrameReg)
257 .addReg(FrameReg)
262 .addReg(FrameReg)
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 157 unsigned FrameReg = getFrameRegister(MF); local
201 dstReg).addReg(FrameReg).addReg(dstReg);
205 dstReg).addReg(FrameReg).addImm(Offset);
230 resReg).addReg(FrameReg).addReg(resReg);
234 resReg).addReg(FrameReg).addImm(Offset);
250 resReg).addReg(FrameReg).addReg(resReg);
256 resReg).addReg(FrameReg).addImm(Offset);
266 dstReg).addReg(FrameReg).addReg(dstReg);
274 MI.getOperand(i).ChangeToRegister(FrameReg, false);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.h | 64 unsigned &FrameReg) const;
|
| H A D | X86FrameLowering.cpp | 1203 unsigned &FrameReg) const {
1210 FrameReg = RegInfo->getBaseRegister();
1212 FrameReg = RegInfo->getStackRegister();
1214 FrameReg = RegInfo->getFrameRegister(MF);
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| H A D | X86ISelLowering.cpp | 10253 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; local
10254 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
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| /external/llvm/include/llvm/Target/ |
| H A D | TargetFrameLowering.h | 170 /// returned directly, and the base register is returned via FrameReg.
172 unsigned &FrameReg) const;
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfCompileUnit.cpp | 1377 unsigned FrameReg = 0; local
1382 FrameReg);
1383 MachineLocation Location(FrameReg, Offset);
1420 unsigned FrameReg = 0; local
1423 TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg);
1424 MachineLocation Location(FrameReg, Offset);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1090 unsigned FrameReg = SP::I6; local
1096 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1100 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 5914 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) : local
5916 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
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