Searched refs:MCID (Results 1 - 25 of 42) sorted by relevance

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/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h96 namespace MCID { namespace in namespace:llvm
190 return Flags & (1 << MCID::Variadic);
196 return Flags & (1 << MCID::HasOptionalDef);
203 return Flags & (1 << MCID::Pseudo);
207 return Flags & (1 << MCID::Return);
211 return Flags & (1 << MCID::Call);
218 return Flags & (1 << MCID::Barrier);
228 return Flags & (1 << MCID::Terminator);
236 return Flags & (1 << MCID::Branch);
242 return Flags & (1 << MCID
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/external/llvm/lib/Target/
H A DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
37 if (OpNum >= MCID.getNumOperands())
40 short RegClass = MCID.OpInfo[OpNum].RegClass;
41 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h197 const MCInstrDesc &MCID) {
198 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL));
206 const MCInstrDesc &MCID,
208 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL))
219 const MCInstrDesc &MCID,
221 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
229 const MCInstrDesc &MCID,
231 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
239 const MCInstrDesc &MCID,
243 return BuildMI(BB, MII, DL, MCID, DestRe
195 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID) argument
204 BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
216 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
226 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
236 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
254 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
263 BuildMI(MachineBasicBlock &BB, MachineBasicBlock::instr_iterator I, DebugLoc DL, const MCInstrDesc &MCID) argument
272 BuildMI(MachineBasicBlock &BB, MachineInstr *I, DebugLoc DL, const MCInstrDesc &MCID) argument
289 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID) argument
299 BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) argument
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H A DMachineInstr.h65 const MCInstrDesc *MCID; // Instruction descriptor. member in class:llvm::MachineInstr
98 /// MCID NULL and no operands.
108 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
113 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
118 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
125 const MCInstrDesc &MCID);
254 const MCInstrDesc &getDesc() const { return *MCID; }
258 int getOpcode() const { return MCID->Opcode; }
326 return hasProperty(MCID::Variadic, Type);
332 return hasProperty(MCID
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/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
26 unsigned Opcode = MCID.getOpcode();
43 const MCInstrDesc &MCID = MI->getDesc(); local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
H A DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); local
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
481 const MCInstrDesc &MCID = MI.getDesc(); local
483 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
817 const MCInstrDesc &MCID = MI.getDesc(); local
825 Binary |= getAddrModeSBit(MI, MCID);
844 const MCInstrDesc &MCID = MI.getDesc(); local
853 Binary |= getAddrModeSBit(MI, MCID);
1010 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1093 const MCInstrDesc &MCID = MI.getDesc(); local
1196 const MCInstrDesc &MCID = MI.getDesc(); local
1280 const MCInstrDesc &MCID = MI.getDesc(); local
1365 const MCInstrDesc &MCID = MI.getDesc(); local
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H A DThumb2SizeReduction.cpp192 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { argument
193 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
512 const MCInstrDesc &MCID = MI->getDesc(); local
513 if (MCID.hasOptionalDef() &&
514 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
656 const MCInstrDesc &MCID = MI->getDesc(); local
657 if (MCID.hasOptionalDef()) {
658 unsigned NumOps = MCID.getNumOperands();
684 unsigned NumOps = MCID.getNumOperands();
686 if (i < NumOps && MCID
715 const MCInstrDesc &MCID = MI->getDesc(); local
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H A DMLxExpansionPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); local
141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
144 unsigned Opcode = MCID.getOpcode();
278 const MCInstrDesc &MCID = MI->getDesc(); local
286 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
296 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
H A DThumb2ITBlockPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); local
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); local
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
360 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
361 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
/external/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
129 if (MCID == NULL) {
133 unsigned idx = MCID->getSchedClass();
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
185 assert(MCID && "The scheduler must filter non-machineinstrs");
186 if (DAG->TII->isZeroCost(MCID->Opcode))
193 unsigned idx = MCID->getSchedClass();
H A DMachineInstr.cpp520 /// MCID NULL and no operands.
522 : MCID(0), Flags(0), AsmPrinterFlags(0),
530 if (MCID->ImplicitDefs)
531 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
533 if (MCID->ImplicitUses)
534 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
542 : MCID(&tid), Flags(0), AsmPrinterFlags(0),
546 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
547 Operands.reserve(NumImplicitOps + MCID
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H A DTargetInstrInfoImpl.cpp63 const MCInstrDesc &MCID = MI->getDesc(); local
64 bool HasDef = MCID.getNumDefs();
128 const MCInstrDesc &MCID = MI->getDesc(); local
129 if (!MCID.isCommutable())
133 SrcOpIdx1 = MCID.getNumDefs();
163 const MCInstrDesc &MCID = MI->getDesc(); local
168 if (MCID.OpInfo[i].isPredicate()) {
H A DMachineVerifier.cpp745 const MCInstrDesc &MCID = MI->getDesc(); local
746 if (MI->getNumOperands() < MCID.getNumOperands()) {
748 *OS << MCID.getNumOperands() << " operands expected, but "
789 const MCInstrDesc &MCID = MI->getDesc(); local
791 // The first MCID.NumDefs operands must be explicit register defines
792 if (MONum < MCID.getNumDefs()) {
793 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
800 } else if (MONum < MCID.getNumOperands()) {
801 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
805 !(MI->isVariadic() && MONum == MCID
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H A DPeepholeOptimizer.cpp415 const MCInstrDesc &MCID = MI->getDesc(); local
416 if (MCID.getNumDefs() != 1)
435 const MCInstrDesc &MCID = MI->getDesc(); local
438 if (MCID.getNumDefs() != 1)
H A DExecutionDepsFix.cpp455 const MCInstrDesc &MCID = MI->getDesc(); local
457 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); local
28 if (!MCID)
94 const MCInstrDesc &MCID = TII.get(Opcode); local
96 isLoad = MCID.mayLoad();
97 isStore = MCID.mayStore();
99 uint64_t TSFlags = MCID.TSFlags;
H A DPPCInstrInfo.cpp433 const MCInstrDesc &MCID = get(Opc); local
434 if (MCID.getNumOperands() == 3)
435 BuildMI(MBB, I, DL, MCID, DestReg)
438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc(); local
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
253 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
259 if (MCID.isCommutable())
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
427 unsigned NumRes = MCID.getNumDefs();
428 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
503 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
504 if (!MCID
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H A DScheduleDAGRRList.cpp982 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
983 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
984 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
989 if (MCID.isCommutable())
1169 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); local
1170 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
1171 unsigned NumRes = MCID.getNumDefs();
1172 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
1295 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); local
1296 if (!MCID
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H A DInstrEmitter.cpp305 const MCInstrDesc &MCID = MI->getDesc(); local
306 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
307 MCID.OpInfo[IIOpNum].isOptionalDef();
317 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
807 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
808 UsedRegs.append(MCID.getImplicitUses(),
809 MCID.getImplicitUses() + MCID.getNumImplicitUses());
H A DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc);
300 if (MCID.mayLoad())
434 const MCInstrDesc &MCID = TII->get(Opc);
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
441 if (MCID.isCommutable())
/external/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp239 MCInstrDesc MCID = MI->getDesc(); local
240 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() :
H A DMipsInstrInfo.cpp177 const MCInstrDesc &MCID = get(Opc); local
178 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);

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