/external/llvm/include/llvm/MC/ |
H A D | MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const { 32 return Info->get(Inst.getOpcode()).isBranch(); 35 virtual bool isConditionalBranch(const MCInst &Inst) const { 36 return Info->get(Inst.getOpcode()).isConditionalBranch(); 39 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 40 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); 43 virtual bool isIndirectBranch(const MCInst &Inst) const { 44 return Info->get(Inst.getOpcode()).isIndirectBranch(); 47 virtual bool isCall(const MCInst &Inst) const { 48 return Info->get(Inst [all...] |
H A D | MCInstBuilder.h | 23 MCInst Inst; member in class:llvm::MCInstBuilder 28 Inst.setOpcode(Opcode); 33 Inst.addOperand(MCOperand::CreateReg(Reg)); 39 Inst.addOperand(MCOperand::CreateImm(Val)); 45 Inst.addOperand(MCOperand::CreateFPImm(Val)); 51 Inst.addOperand(MCOperand::CreateExpr(Val)); 57 Inst.addOperand(MCOperand::CreateInst(Val)); 62 return Inst;
|
/external/llvm/lib/MC/ |
H A D | MCInstrAnalysis.cpp | 13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 15 if (Inst.getNumOperands() == 0 || 16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 19 int64_t Imm = Inst.getOperand(0).getImm();
|
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, 92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, 95 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, 98 static DecodeStatus Decode2RInstruction(MCInst &Inst, 103 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, 108 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, 113 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, 118 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, 123 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, 128 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, 205 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 217 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 228 DecodeMEMiiOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 270 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 340 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 353 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 366 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 379 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 393 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 406 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 419 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 433 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 504 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 518 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 532 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 545 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 558 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 571 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 584 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 598 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 613 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 627 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 641 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 661 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 675 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 695 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 714 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsDirectObjLower.h | 23 void LowerLargeShift(MCInst &Inst); 24 void LowerDextDins(MCInst &Inst);
|
H A D | MipsDirectObjLower.cpp | 23 void Mips::LowerLargeShift(MCInst& Inst) { argument 25 assert(Inst.getNumOperands() == 3 && "Invalid no. of operands for shift!"); 26 assert(Inst.getOperand(2).isImm()); 28 int64_t Shift = Inst.getOperand(2).getImm(); 34 Inst.getOperand(2).setImm(Shift); 36 switch (Inst.getOpcode()) { 41 Inst.setOpcode(Mips::DSLL32); 44 Inst.setOpcode(Mips::DSRL32); 47 Inst.setOpcode(Mips::DSRA32);
|
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 91 static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst, 96 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, 101 static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, 106 static DecodeStatus DecodeDSPRegsRegisterClass(MCInst &Inst, 111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, 116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, 121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, 126 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, 131 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, 136 static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, 330 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 339 DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 352 DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 363 DecodeDSPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 370 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 382 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 394 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 402 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 424 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 443 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 454 DecodeCondCode(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 463 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 476 DecodeHWRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 487 DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 499 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument 509 DecodeBC1(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 519 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 530 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 538 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 549 DecodeExtSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/clang/test/Parser/ |
H A D | cxx-default-args.cpp | 10 typedef struct Inst { struct
|
/external/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 50 Instruction *Inst; member in struct:__anon9916::SimpleValue 52 SimpleValue(Instruction *I) : Inst(I) { 53 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!"); 57 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() || 58 Inst == DenseMapInfo<Instruction*>::getTombstoneKey(); 61 static bool canHandle(Instruction *Inst) { argument 63 if (CallInst *CI = dyn_cast<CallInst>(Inst)) 65 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) || 66 isa<GetElementPtrInst>(Inst) || is 93 Instruction *Inst = Val.Inst; local 198 Instruction *Inst; member in struct:__anon9917::CallValue 209 canHandle(Instruction *Inst) argument 240 Instruction *Inst = Val.Inst; local 432 Instruction *Inst = I++; local 537 << *Inst << '\\n'); local [all...] |
H A D | Sink.cpp | 58 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const; 59 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const; 74 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument 80 for (Value::use_iterator I = Inst->use_begin(), 81 E = Inst->use_end(); I != E; ++I) { 136 Instruction *Inst = I; // The instruction to sink. local 144 if (isa<DbgInfoIntrinsic>(Inst)) 147 if (SinkInstruction(Inst, Stores)) 156 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument 159 if (Inst 180 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument 219 SinkInstruction(Instruction *Inst, SmallPtrSet<Instruction *, 8> &Stores) argument [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 159 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 161 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 163 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 165 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 167 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 169 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 171 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 175 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigne 898 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 909 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 921 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 928 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 958 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 975 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 996 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1006 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1014 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1029 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1049 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1070 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1082 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1096 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1105 DecodeSOImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1114 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1151 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1186 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1221 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1238 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1257 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1284 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1429 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1534 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 1578 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1769 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1798 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1883 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1923 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1963 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 1987 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2013 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2041 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2061 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2080 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2086 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2113 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2139 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2156 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2430 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2701 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2748 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2796 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2831 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2886 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2931 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 2950 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2956 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2962 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2968 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 2974 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3010 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3034 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3042 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3050 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3058 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3073 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3087 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3097 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3105 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3122 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3177 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3191 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3206 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument 3221 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3234 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3265 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3295 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3310 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3321 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3346 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument 3357 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3370 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3394 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3404 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3420 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3462 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3494 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3502 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3525 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3534 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 3541 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3564 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3591 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3616 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3644 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3669 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3694 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3761 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3827 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3894 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 3958 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4028 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4092 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4173 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4245 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4271 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4297 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4319 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4356 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4390 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument 4405 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 4416 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4443 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4471 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 4499 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 4526 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/tools/llvm-objdump/ |
H A D | MCFunction.cpp | 55 MCInst Inst; local 56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){ 57 Instructions.push_back(MCDecodedInst(Index, Size, Inst)); 58 if (Ana->isBranch(Inst)) { 59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 72 } else if (Ana->isReturn(Inst)) { 76 } else if (Ana->isCall(Inst)) { 77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size); 116 const MCDecodedInst &Inst = BB.getInsts().back(); local 118 if (Ana->isBranch(Inst [all...] |
H A D | MCFunction.h | 35 MCInst Inst; member in struct:llvm::MCDecodedInst 38 MCDecodedInst(uint64_t Address, uint64_t Size, MCInst Inst) argument 39 : Address(Address), Size(Size), Inst(Inst) {} 61 void addInst(const MCDecodedInst &Inst) { Insts.push_back(Inst); } argument
|
/external/llvm/utils/TableGen/ |
H A D | InstrInfoEmitter.cpp | 48 void emitRecord(const CodeGenInstruction &Inst, unsigned Num, 56 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst); 73 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument 76 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { 85 DagInit *MIOI = Inst.Operands[i].MIOperandInfo; 89 OperandList.push_back(Inst.Operands[i]); 91 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) { 92 OperandList.push_back(Inst.Operands[i]); 122 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) 127 if (Inst 206 Record *Inst = (*II)->TheDef; local 298 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 66 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 69 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 72 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 75 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, 78 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 80 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 82 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 84 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, 86 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, 89 static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, 240 DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 251 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 261 DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 273 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 284 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 295 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 307 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 318 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 330 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 341 DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 351 DecodeAddrRegExtendOperand(llvm::MCInst &Inst, unsigned OptionHiS, uint64_t Address, const void *Decoder) argument 364 DecodeBitfield32ImmOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument 377 DecodeCVT32FixedPosOperand(llvm::MCInst &Inst, unsigned Imm6Bits, uint64_t Address, const void *Decoder) argument 389 DecodeFPZeroOperand(llvm::MCInst &Inst, unsigned RmBits, uint64_t Address, const void *Decoder) argument 402 DecodeMoveWideImmOperand(llvm::MCInst &Inst, unsigned FullImm, uint64_t Address, const void *Decoder) argument 417 DecodeLogicalImmOperand(llvm::MCInst &Inst, unsigned Bits, uint64_t Address, const void *Decoder) argument 430 DecodeRegExtendOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument 442 Decode32BitShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount, uint64_t Address, const void *Decoder) argument 454 DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 546 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 570 DecodeLDSTPairInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument 654 DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument 690 DecodeNamedImmOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 705 DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper, llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 718 DecodeMRSOperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 726 DecodeMSROperand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument 734 DecodeSingleIndexedInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 188 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 189 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &); 190 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, 192 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, 194 void cvtLdWriteBackRegAddrMode2(MCInst &Inst, 196 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, 198 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst, 200 void cvtStWriteBackRegAddrMode2(MCInst &Inst, 202 void cvtStWriteBackRegAddrMode3(MCInst &Inst, 204 void cvtLdExtTWriteBackImm(MCInst &Inst, 1429 addExpr(MCInst &Inst, const MCExpr *Expr) const argument 1439 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1446 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument 1451 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument 1456 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument 1461 addITMaskOperands(MCInst &Inst, unsigned N) const argument 1466 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument 1471 addCCOutOperands(MCInst &Inst, unsigned N) const argument 1476 addRegOperands(MCInst &Inst, unsigned N) const argument 1481 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument 1491 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument 1502 addShifterImmOperands(MCInst &Inst, unsigned N) const argument 1508 addRegListOperands(MCInst &Inst, unsigned N) const argument 1516 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument 1520 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument 1524 addRotImmOperands(MCInst &Inst, unsigned N) const argument 1530 addBitfieldOperands(MCInst &Inst, unsigned N) const argument 1541 addImmOperands(MCInst &Inst, unsigned N) const argument 1546 addFBits16Operands(MCInst &Inst, unsigned N) const argument 1552 addFBits32Operands(MCInst &Inst, unsigned N) const argument 1558 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1565 addImm8s4Operands(MCInst &Inst, unsigned N) const argument 1573 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument 1581 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument 1589 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument 1597 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1605 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1613 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument 1622 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument 1631 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument 1639 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument 1647 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument 1655 addARMSOImmNotOperands(MCInst &Inst, unsigned N) const argument 1663 addARMSOImmNegOperands(MCInst &Inst, unsigned N) const argument 1671 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument 1676 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument 1681 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument 1689 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument 1705 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument 1711 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument 1929 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument 1936 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument 1943 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument 1950 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument 1961 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument 1973 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument 1979 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument 1990 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument 1995 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument 2000 addVecListOperands(MCInst &Inst, unsigned N) const argument 2005 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument 2011 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument 2016 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument 2021 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument 2026 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument 2034 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument 2046 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument 2060 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument 2074 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument 2088 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument 3926 cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3943 cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3960 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3975 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 3988 cvtLdWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4003 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4019 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4032 cvtStWriteBackRegAddrMode2(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4045 cvtStWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4058 cvtLdExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4076 cvtLdExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4094 cvtStExtTWriteBackImm(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4112 cvtStExtTWriteBackReg(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4130 cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4147 cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4164 cvtLdWriteBackRegAddrMode3(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4177 cvtThumbMultiply(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4194 cvtVLDwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4207 cvtVLDwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4222 cvtVSTwbFixed(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 4235 cvtVSTwbRegister(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5246 checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument 5262 listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) argument 5283 validateInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 5716 processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) argument 7487 checkTargetMatchPredicate(MCInst &Inst) argument 7535 MCInst Inst; local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.h | 19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate 21 Inst(unsigned Opc, unsigned ImmOpnd); 23 typedef SmallVector<Inst, 7 > InstSeq; 33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
|
/external/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCExpand.cpp | 98 Instruction *Inst = &*I; local 100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n"); 102 switch (GetBasicInstructionClass(Inst)) { 114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0); 115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n" 117 Inst->replaceAllUsesWith(Value);
|
H A D | DependencyAnalysis.cpp | 35 llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument 47 ImmutableCallSite CS = static_cast<const Value *>(Inst); 71 llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument 79 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) { 85 } else if (ImmutableCallSite CS = static_cast<const Value *>(Inst)) { 94 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 104 for (User::const_op_iterator OI = Inst->op_begin(), OE = Inst->op_end(); 113 /// Test if there can be dependencies on Inst through Arg. This function only 116 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst, argument 236 Instruction *Inst = --LocalStartPos; local [all...] |
H A D | DependencyAnalysis.h | 61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, 67 CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA, 73 CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
|
H A D | ObjCARCAPElim.cpp | 98 Instruction *Inst = I++; local 99 switch (GetBasicInstructionClass(Inst)) { 101 Push = Inst; 106 if (Push && cast<CallInst>(Inst)->getArgOperand(0) == Push) { 110 " Pop: " << *Inst << "\n" 112 Inst->eraseFromParent(); 118 if (MayAutorelease(ImmutableCallSite(Inst)))
|
/external/llvm/lib/Analysis/ |
H A D | PHITransAddr.cpp | 25 static bool CanPHITrans(Instruction *Inst) { argument 26 if (isa<PHINode>(Inst) || 27 isa<GetElementPtrInst>(Inst)) 30 if (isa<CastInst>(Inst) && 31 isSafeToSpeculativelyExecute(Inst)) 34 if (Inst->getOpcode() == Instruction::Add && 35 isa<ConstantInt>(Inst->getOperand(1))) 118 Instruction *Inst = dyn_cast<Instruction>(Addr); local 119 return Inst == 0 || CanPHITrans(Inst); 149 Instruction *Inst = dyn_cast<Instruction>(V); local [all...] |
H A D | MemDepPrinter.cpp | 102 Instruction *Inst = &*I; local 104 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory()) 107 MemDepResult Res = MDA.getDependency(Inst); 109 Deps[Inst].insert(std::make_pair(getInstTypePair(Res), 111 } else if (CallSite CS = cast<Value>(Inst)) { 115 DepSet &InstDeps = Deps[Inst]; 123 if (LoadInst *LI = dyn_cast<LoadInst>(Inst)) { 126 Deps[Inst].insert(std::make_pair(getInstTypePair(0, Unknown), 132 } else if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) { 162 const Instruction *Inst = &*I; local [all...] |
/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeAsmBackend.cpp | 53 bool mayNeedRelaxation(const MCInst &Inst) const; 60 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 78 bool MBlazeAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 79 if (getRelaxedOpcode(Inst.getOpcode()) == Inst.getOpcode()) 83 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) 84 hasExprOrImm |= Inst.getOperand(i).isExpr(); 101 void MBlazeAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument 102 Res = Inst; 103 Res.setOpcode(getRelaxedOpcode(Inst [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 118 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 119 if (Inst.getOpcode() == AArch64::Bcc 120 && Inst.getOperand(0).getImm() == A64CC::AL) 122 return MCInstrAnalysis::isUnconditionalBranch(Inst); 125 virtual bool isConditionalBranch(const MCInst &Inst) const { 126 if (Inst.getOpcode() == AArch64::Bcc 127 && Inst.getOperand(0).getImm() == A64CC::AL) 129 return MCInstrAnalysis::isConditionalBranch(Inst); 132 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr, argument 134 unsigned LblOperand = Inst [all...] |