Searched refs:Cond (Results 1 - 25 of 156) sorted by relevance

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/external/clang/test/SemaTemplate/
H A Dvalue-dependent-null-pointer-constant.cpp5 const char *f0(bool Cond) { argument
6 return Cond? "honk" : N;
9 const char *f1(bool Cond) { argument
10 return Cond? N : "honk";
H A Doverload-candidates.cpp52 template<typename Cond, typename T = void> struct enable_if : boost::enable_if<Cond::value, T> {};
H A Dinstantiate-expr-2.cpp77 struct Cond {
81 enum { resultT = Cond<true>::is,
82 resultF = Cond<false>::is };
92 struct Cond { struct in namespace:N6
97 typedef Cond<true, int, char>::True True;
98 typedef Cond<true, int, char>::False False;
112 struct Cond { struct in namespace:N7
117 //Cond<true, int*, double> C; // Errors
119 //typedef Cond<true, int*, double>::Type Type; // Errors
120 typedef Cond<tru
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H A Dconstructor-template.cpp60 X2 test(bool Cond, X2 x2) { argument
61 if (Cond)
80 X4 test_X4(bool Cond, X4 x4) { argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp118 SmallVectorImpl<MachineOperand> &Cond,
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
147 Cond.push_back(LastInst->getOperand(0));
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
166 Cond.push_back(SecondLastInst->getOperand(0));
189 const SmallVectorImpl<MachineOperand> &Cond,
193 assert((Cond.size() == 2 || Cond.size() == 0) &&
197 if (!Cond.empty())
198 Opc = (unsigned)Cond[
115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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/external/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp79 SmallVectorImpl<MachineOperand> &Cond) const {
86 Cond.push_back(MachineOperand::CreateImm(Opc));
89 Cond.push_back(Inst->getOperand(i));
95 SmallVectorImpl<MachineOperand> &Cond,
98 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
105 const SmallVectorImpl<MachineOperand>& Cond)
107 unsigned Opc = Cond[0].getImm();
111 for (unsigned i = 1; i < Cond.size(); ++i) {
112 if (Cond[i].isReg())
113 MIB.addReg(Cond[
92 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
123 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
190 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr*> &BranchInstrs) const argument
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H A DMipsInstrInfo.h50 SmallVectorImpl<MachineOperand> &Cond,
57 const SmallVectorImpl<MachineOperand> &Cond,
61 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
65 SmallVectorImpl<MachineOperand> &Cond,
100 SmallVectorImpl<MachineOperand> &Cond) const;
103 const SmallVectorImpl<MachineOperand>& Cond) const;
/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DConstraintManager.h68 DefinedSVal Cond,
75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument
76 ProgramStateRef StTrue = assume(State, Cond, true);
78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary
86 assert(assume(State, Cond, false) && "System is over constrained.");
91 ProgramStateRef StFalse = assume(State, Cond, false);
/external/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.h36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond,
39 ProgramStateRef assume(ProgramStateRef state, Loc Cond, bool Assumption);
41 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption);
89 Loc Cond,
93 NonLoc Cond,
H A DSimpleConstraintManager.cpp59 DefinedSVal Cond,
61 if (Optional<NonLoc> NV = Cond.getAs<NonLoc>())
63 return assume(state, Cond.castAs<Loc>(), Assumption);
75 Loc Cond, bool Assumption) {
76 switch (Cond.getSubKind()) {
84 const MemRegion *R = Cond.castAs<loc::MemRegionVal>().getRegion();
106 bool b = Cond.castAs<loc::ConcreteInt>().getValue() != 0;
156 NonLoc Cond,
161 if (!canReasonAbout(Cond)) {
163 SymbolRef sym = Cond
58 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument
74 assumeAux(ProgramStateRef state, Loc Cond, bool Assumption) argument
155 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp189 SmallVectorImpl<MachineOperand> &Cond,
222 Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(MachineOperand::CreateImm(BranchCode));
245 Cond.push_back(SecondLastInst->getOperand(0));
277 const SmallVectorImpl<MachineOperand> &Cond,
281 assert((Cond.size() == 2 || Cond.size() == 0) &&
285 if (Cond.empty()) {
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[
187 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
275 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DXCoreInstrInfo.h54 SmallVectorImpl<MachineOperand> &Cond,
59 const SmallVectorImpl<MachineOperand> &Cond,
88 SmallVectorImpl<MachineOperand> &Cond) const;
/external/clang/test/SemaCXX/
H A Dvector.cpp40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument
43 __typeof__(Cond? c16 : c16) *c16p1 = &c16;
44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16;
45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e;
46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e;
49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e;
50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e;
51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e;
52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e;
55 (void)(Cond
108 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument
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/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.h74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
78 SmallVectorImpl<MachineOperand> &Cond,
84 const SmallVectorImpl<MachineOperand> &Cond,
H A DMSP430InstrInfo.cpp127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
128 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
154 Cond[0].setImm(CC);
172 SmallVectorImpl<MachineOperand> &Cond,
207 Cond.clear();
231 if (Cond.empty()) {
234 Cond.push_back(MachineOperand::CreateImm(BranchCode));
240 assert(Cond.size() == 1);
248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[
169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
260 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DMSP430BranchSelector.cpp150 SmallVector<MachineOperand, 1> Cond; local
151 Cond.push_back(I->getOperand(1));
154 TII->ReverseBranchCondition(Cond);
156 .addImm(4).addOperand(Cond[0]);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp182 SmallVectorImpl<MachineOperand> &Cond,
200 Cond.push_back(LastInst->getOperand(0));
219 Cond.push_back(SecondLastInst->getOperand(0));
264 const SmallVectorImpl<MachineOperand> &Cond,
268 assert((Cond.size() == 1 || Cond.size() == 0) &&
273 if (Cond.empty()) // Unconditional branch
277 .addReg(Cond[0].getReg()).addMBB(TBB);
283 .addReg(Cond[0].getReg()).addMBB(TBB);
179 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
262 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
H A DNVPTXInstrInfo.h68 SmallVectorImpl<MachineOperand> &Cond,
73 const SmallVectorImpl<MachineOperand> &Cond,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp210 SmallVectorImpl<MachineOperand> &Cond,
242 Cond.push_back(LastInst->getOperand(0));
243 Cond.push_back(LastInst->getOperand(1));
252 Cond.push_back(MachineOperand::CreateImm(1));
253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
263 Cond.push_back(MachineOperand::CreateImm(0));
264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
288 Cond.push_back(SecondLastInst->getOperand(0));
289 Cond.push_back(SecondLastInst->getOperand(1));
301 Cond
208 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
371 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DPPCInstrInfo.h116 SmallVectorImpl<MachineOperand> &Cond,
121 const SmallVectorImpl<MachineOperand> &Cond,
147 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h75 SmallVectorImpl<MachineOperand> &Cond,
82 const SmallVectorImpl<MachineOperand> &Cond,
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp140 /// setting TBB to the destination basic block and populating the Cond vector
145 SmallVectorImpl<MachineOperand> &Cond) {
154 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
155 Cond.push_back(I->getOperand(0));
163 Cond.push_back(MachineOperand::CreateImm(I->getOpcode()));
164 Cond.push_back(I->getOperand(0));
165 Cond.push_back(I->getOperand(1));
177 SmallVectorImpl<MachineOperand> &Cond,
203 classifyCondBranch(LastInst, TBB, Cond);
239 Cond
144 classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB, SmallVectorImpl<MachineOperand> &Cond) argument
175 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument
304 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A DAArch64InstrInfo.h63 SmallVectorImpl<MachineOperand> &Cond,
67 const SmallVectorImpl<MachineOperand> &Cond,
70 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1068 ISD::CondCode Cond, bool foldBooleans,
1073 switch (Cond) {
1084 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1097 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1099 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1102 Cond = ISD::SETNE;
1106 Cond = ISD::SETEQ;
1110 Zero, Cond);
1127 if ((Cond
1067 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, DebugLoc dl) const argument
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/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h775 inline bool isTrueWhenEqual(CondCode Cond) { argument
776 return ((int)Cond & 1) != 0;
783 inline unsigned getUnorderedFlavor(CondCode Cond) { argument
784 return ((int)Cond >> 3) & 3;

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