/external/llvm/lib/Analysis/ |
H A D | InstructionSimplify.cpp | 137 if (BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS)) 138 if (Op0->getOpcode() == OpcodeToExpand) { 140 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1), *C = RHS; 197 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); 200 if (!Op0 || Op0->getOpcode() != OpcodeToExtract || 205 Value *A = Op0->getOperand(0), *B = Op0->getOperand(1); 268 BinaryOperator *Op0 592 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 653 SimplifyAddInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 733 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 858 SimplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 867 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 909 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 945 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const Query &Q, unsigned MaxRecurse) argument 973 SimplifyMulInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1036 SimplifyFAddInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1042 SimplifyFSubInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1048 SimplifyFMulInst(Value *Op0, Value *Op1, FastMathFlags FMF, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1056 SimplifyMulInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1064 SimplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1136 SimplifySDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1144 SimplifySDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1152 SimplifyUDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1160 SimplifyUDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1166 SimplifyFDivInst(Value *Op0, Value *Op1, const Query &Q, unsigned) argument 1179 SimplifyFDivInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1187 SimplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1241 SimplifySRemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1249 SimplifySRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1257 SimplifyURemInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1265 SimplifyURemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1271 SimplifyFRemInst(Value *Op0, Value *Op1, const Query &, unsigned) argument 1284 SimplifyFRemInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1292 SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1336 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const Query &Q, unsigned MaxRecurse) argument 1352 SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1361 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1379 SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1389 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const Query &Q, unsigned MaxRecurse) argument 1411 SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1421 SimplifyAndInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1512 SimplifyAndInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1520 SimplifyOrInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1606 SimplifyOrInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument 1614 SimplifyXorInst(Value *Op0, Value *Op1, const Query &Q, unsigned MaxRecurse) argument 1666 SimplifyXorInst(Value *Op0, Value *Op1, const DataLayout *TD, const TargetLibraryInfo *TLI, const DominatorTree *DT) argument [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineMulDivRem.cpp | 100 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 102 if (Value *V = SimplifyMulInst(Op0, Op1, TD)) 109 return BinaryOperator::CreateNeg(Op0, I.getName()); 114 if (BinaryOperator *SI = dyn_cast<BinaryOperator>(Op0)) 122 Constant *NewCst = ConstantInt::get(Op0->getType(), Val.logBase2()); 123 BinaryOperator *Shl = BinaryOperator::CreateShl(Op0, NewCst); 131 if (Op0->hasOneUse() && 132 match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) { 146 if (Op0->hasOneUse()) { 149 if (match(Op0, m_Su 372 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 613 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 678 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 764 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 845 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 961 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 993 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1036 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1107 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 31 if (isa<Constant>(Op0)) 37 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I)) 312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1, argument 320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) { 322 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n"); 325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this)); 331 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits(); 338 return ReplaceInstUsesWith(I, Constant::getNullValue(Op0->getType())); 345 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0)) [all...] |
H A D | InstCombineAndOrXor.cpp | 714 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 717 return getNewICmpValue(isSigned, Code, Op0, Op1, Builder); 1012 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1014 if (Value *V = SimplifyAndInst(Op0, Op1, TD)) 1030 if (BinaryOperator *Op0I = dyn_cast<BinaryOperator>(Op0)) { 1109 if (match(Op0, m_Trunc(m_And(m_Value(X), m_ConstantInt(YC))))) { 1122 if (SelectInst *SI = dyn_cast<SelectInst>(Op0)) 1125 if (isa<PHINode>(Op0)) 1132 if (Value *Op0NotVal = dyn_castNotVal(Op0)) 1134 if (Op0 1469 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local 1756 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2093 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 2327 Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1); local [all...] |
H A D | InstCombineCompares.cpp | 1841 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1846 if (getComplexity(Op0) < getComplexity(Op1)) { 1848 std::swap(Op0, Op1); 1852 if (Value *V = SimplifyICmpInst(I.getPredicate(), Op0, Op1, TD)) 1860 if (match(Op0, m_Select(m_Value(Cond), m_Value(SelectTrue), 1873 Type *Ty = Op0->getType(); 1880 Value *Xor = Builder->CreateXor(Op0, Op1, I.getName()+"tmp"); 1884 return BinaryOperator::CreateXor(Op0, Op1); 1887 std::swap(Op0, Op1); // Change icmp ugt -> icmp ult 1890 Value *Not = Builder->CreateNot(Op0, 2905 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstCombineAddSub.cpp | 1281 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local 1283 if (Value *V = SimplifySubInst(Op0, Op1, I.hasNoSignedWrap(), 1293 BinaryOperator *Res = BinaryOperator::CreateAdd(Op0, V); 1300 return BinaryOperator::CreateXor(Op0, Op1); 1303 if (match(Op0, m_AllOnes())) 1306 if (ConstantInt *C = dyn_cast<ConstantInt>(Op0)) { 1354 if (match(Op1, m_Add(m_Specific(Op0), m_Value(Y))) || 1355 match(Op1, m_Add(m_Value(Y), m_Specific(Op0)))) 1359 if (match(Op0, m_Sub(m_Specific(Op1), m_Value(Y)))) 1370 return BinaryOperator::CreateAdd(Op0, 1449 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); local [all...] |
H A D | InstructionCombining.cpp | 213 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(I.getOperand(0)); local 218 if (Op0 && Op0->getOpcode() == Opcode) { 219 Value *A = Op0->getOperand(0); 220 Value *B = Op0->getOperand(1); 231 (!Op0 || (isa<BinaryOperator>(Op0) && Op0->hasNoSignedWrap()))) { 233 // the operands to Op0. 269 if (Op0 398 BinaryOperator *Op0 = dyn_cast<BinaryOperator>(LHS); local 565 Value *Op0 = SO, *Op1 = ConstOperand; local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 188 unsigned Op0, bool Op0IsKill); 197 unsigned Op0, bool Op0IsKill, 207 unsigned Op0, bool Op0IsKill, 217 unsigned Op0, bool Op0IsKill, 227 unsigned Op0, bool Op0IsKill, 237 unsigned Op0, bool Op0IsKill, 267 unsigned Op0, bool Op0IsKill); 274 unsigned Op0, bool Op0IsKill, 282 unsigned Op0, bool Op0IsKill, 291 unsigned Op0, boo [all...] |
/external/llvm/include/llvm/Support/ |
H A D | GetElementPtrTypeIterator.h | 102 gep_type_begin(Type *Op0, ArrayRef<T> A) { argument 103 return generic_gep_type_iterator<const T *>::begin(Op0, A.begin()); 108 gep_type_end(Type *Op0, ArrayRef<T> A) { argument
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H A D | PatternMatch.h | 988 m_Intrinsic(const T0 &Op0) { argument 989 return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0)); 994 m_Intrinsic(const T0 &Op0, const T1 &Op1) { argument 995 return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1)); 1000 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) { argument 1001 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2)); 1006 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1007 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3)); 1013 m_BSwap(const Opnd0 &Op0) { argument 1014 return m_Intrinsic<Intrinsic::bswap>(Op0); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 402 unsigned Op0 = getRegForValue(I->getOperand(0)); local 403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 439 ISDOpcode, Op0, Op0IsKill, CF); 457 Op0, Op0IsKill, 777 unsigned Op0 = getRegForValue(I->getOperand(0)); local 778 if (Op0 == 0) 793 ResultReg).addReg(Op0); 799 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); 941 const Value *Op0 local 1156 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument 1205 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 1224 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 1245 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 1269 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1290 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument 1313 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument 1334 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 1358 FastEmitInst_rrii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm1, uint64_t Imm2) argument 1415 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1431 FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) argument [all...] |
H A D | TargetLowering.cpp | 1356 SDValue Op0 = N0; local 1357 if (Op0.getOpcode() == ISD::TRUNCATE) 1358 Op0 = Op0.getOperand(0); 1360 if ((Op0.getOpcode() == ISD::XOR) && 1361 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1362 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1365 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1368 if (Op0 [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 192 SDValue Op0, Op1; local 196 if (!SelectADDRrr(Op, Op0, Op1)) 197 SelectADDRri(Op, Op0, Op1); 201 OutOps.push_back(Op0);
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/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 554 Constant *Op0 = CE->getOperand(0); local 558 GenericValue Result = getConstantValue(Op0); 567 GenericValue GV = getConstantValue(Op0); 573 GenericValue GV = getConstantValue(Op0); 579 GenericValue GV = getConstantValue(Op0); 586 GenericValue GV = getConstantValue(Op0); 592 GenericValue GV = getConstantValue(Op0); 597 GenericValue GV = getConstantValue(Op0); 612 GenericValue GV = getConstantValue(Op0); 628 GenericValue GV = getConstantValue(Op0); [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 1165 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 1167 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 1175 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 1180 moveToTop(Op0, I); // Move dead operand to TOS. 1181 TOS = Op0; 1191 duplicateToTop(Op0, Dest, I); 1192 Op0 = TOS = Dest; 1199 duplicateToTop(Op0, Dest, I); 1200 Op0 = TOS = Dest; 1206 assert((TOS == Op0 || TO [all...] |
/external/llvm/include/llvm/Analysis/ |
H A D | InstructionSimplify.h | 128 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, 135 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, 142 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
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H A D | ScalarEvolution.h | 584 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 587 Ops.push_back(Op0); 602 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 605 Ops.push_back(Op0);
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/external/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 163 Value *Op0 = C->getOperand(0); local 164 if (isa<Instruction>(Op0) && 165 cast<Instruction>(Op0)->getParent() == C->getParent())
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/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 1236 GenericValue Op0 = getOperandValue(CE->getOperand(0), SF); 1241 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break; 1242 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break; 1243 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break; 1244 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break; 1245 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break; 1246 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break; 1247 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break; 1248 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break; 1249 case Instruction::SDiv: Dest.IntVal = Op0 [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1464 bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, 1542 /// Copy Op0 and Op1 operands into a new array assigned to MI. 1543 static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0, argument 1546 size_t numMemRefs = (Op0->memoperands_end() - Op0->memoperands_begin()) 1552 std::copy(Op0->memoperands_begin(), Op0->memoperands_end(), MemBegin); 1559 ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, argument 1572 unsigned Opcode = Op0->getOpcode(); 1589 if (!Op0 1721 MachineInstr *Op0 = Ops.back(); local [all...] |
H A D | ARMFastISel.cpp | 108 unsigned Op0, bool Op0IsKill); 111 unsigned Op0, bool Op0IsKill, 115 unsigned Op0, bool Op0IsKill, 120 unsigned Op0, bool Op0IsKill, 124 unsigned Op0, bool Op0IsKill, 128 unsigned Op0, bool Op0IsKill, 139 unsigned Op0, bool Op0IsKill, 304 unsigned Op0, bool Op0IsKill) { 310 .addReg(Op0, Op0IsKill * RegState::Kill)); 313 .addReg(Op0, Op0IsKil 302 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 321 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 343 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument 368 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 390 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument 412 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument 476 FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx) argument 1218 Value *Op0 = I->getOperand(0); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 224 MachineOperand &Op0 = MI->getOperand(0); local 225 unsigned Reg0 = Op0.getReg();
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/external/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.cpp | 502 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local 508 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; 530 uint32_t Op0 = (Bits >> 14) & 0x3; local 538 if (Op0 != 3 || (CRn != 11 && CRn != 15)) { 543 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
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/external/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 272 Value *Op0 = CI->getArgOperand(0); local 293 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 288 SDValue Op0, Op1; local 292 if (!SelectAddr(Op, Op0, Op1)) 297 OutOps.push_back(Op0);
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