/external/clang/test/Parser/ |
H A D | cxx-using-declaration.cpp | 4 int VA; member in namespace:A 9 using A::VA; 15 VA = 1;
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/external/clang/test/Preprocessor/ |
H A D | macro_paste_bad.c | 32 #define VA __VA_ ## ARGS__ macro 33 int VA; // expected-warning {{__VA_ARGS__ can only appear in the expansion of a C99 variadic macro}} variable
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/external/skia/src/sfnt/ |
H A D | SkOTTable_OS_2.h | 31 struct VA : SkOTTableOS2_VA { } vA; struct in union:SkOTTableOS2::Version 45 SK_COMPILE_ASSERT(sizeof(SkOTTableOS2::Version::VA) == 68, sizeof_SkOTTableOS2__VA_not_68);
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/external/clang/test/CXX/special/class.dtor/ |
H A D | p3-0x.cpp | 140 struct VA { struct 142 virtual ~VA() {} 145 struct VB : VA 149 struct TVB : VA
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/external/webkit/Source/WebKit/android/content/ |
H A D | address_detector.cpp | 722 VA = 52, // VA Virginia enumerator in enum:USState 753 DC, VA, DC, DC, DC, DC, MD, MD, MD, MD, // 200-209 755 VA, VA, VA, VA, VA, VA, VA, V [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 105 CCValAssign &VA = RVLocs[i]; local 106 assert(VA.isRegLoc() && "Can only return in registers!"); 108 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 166 CCValAssign &VA = ArgLocs[i]; local 179 if (VA.isRegLoc()) { 180 if (VA.needsCustom()) { 181 assert(VA.getLocVT() == MVT::f64); 183 MF.getRegInfo().addLiveIn(VA 408 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 729 CCValAssign &VA = ArgLocs[i]; local 730 MVT RegVT = VA.getLocVT(); 734 switch (VA.getLocInfo()) { 750 if (VA.isRegLoc()) { 751 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 754 assert(VA.isMemLoc()); 762 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; 763 unsigned StackLoc = VA.getLocMemOffset() + 4; 901 CCValAssign &VA = ArgLocs[i]; local 904 if (VA 1046 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 335 CCValAssign &VA = ArgLocs[i]; local 336 if (VA.isRegLoc()) { 338 EVT RegVT = VA.getLocVT(); 350 RegInfo.addLiveIn(VA.getLocReg(), VReg); 356 if (VA.getLocInfo() == CCValAssign::SExt) 358 DAG.getValueType(VA.getValVT())); 359 else if (VA.getLocInfo() == CCValAssign::ZExt) 361 DAG.getValueType(VA.getValVT())); 363 if (VA.getLocInfo() != CCValAssign::Full) 364 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA 431 CCValAssign &VA = RVLocs[i]; local 487 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 764 CCValAssign &VA = ValLocs[0]; 767 if (VA.getLocInfo() != CCValAssign::Full) 770 if (!VA.isRegLoc()) 775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 778 unsigned SrcReg = Reg + VA.getValNo(); 780 EVT DstVT = VA.getValVT(); 804 unsigned DstReg = VA.getLocReg(); 813 RetRegs.push_back(VA.getLocReg()); 1805 CCValAssign &VA local [all...] |
H A D | X86ISelLowering.h | 755 const CCValAssign &VA, MachineFrameInfo *MFI, 759 const CCValAssign &VA,
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H A D | X86ISelLowering.cpp | 1617 CCValAssign &VA = RVLocs[i]; local 1618 assert(VA.isRegLoc() && "Can only return in registers!"); 1623 if (VA.getLocInfo() == CCValAssign::SExt) 1624 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1625 else if (VA.getLocInfo() == CCValAssign::ZExt) 1626 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1627 else if (VA.getLocInfo() == CCValAssign::AExt) 1628 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1629 else if (VA.getLocInfo() == CCValAssign::BCvt) 1630 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA 1776 CCValAssign &VA = RVLocs[i]; local 1906 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 1987 CCValAssign &VA = ArgLocs[i]; local 2224 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2370 CCValAssign &VA = ArgLocs[i]; local 2501 CCValAssign &VA = ArgLocs[i]; local 2908 CCValAssign &VA = RVLocs[i]; local 2971 CCValAssign &VA = ArgLocs[i]; local 3000 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/qemu/ |
H A D | ppc-dis.c | 820 /* The VA field in a VA, VX or VXR form instruction. */ 821 #define VA UI + 1 824 /* The VB field in a VA, VX or VXR form instruction. */ 825 #define VB VA + 1 828 /* The VC field in a VA form instruction. */ 832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 846 /* The SHB field in a VA form instruction. */ 1723 /* An VA form instruction. */ 1726 /* The mask for an VA for 817 #define VA macro [all...] |
/external/mksh/src/ |
H A D | shf.c | 776 #define VA(type) va_arg(args, type) macro 825 tmp = VA(int); 886 lnum = (long)VA(ssize_t); 888 lnum = VA(long); 890 lnum = (long)(short)VA(int); 892 lnum = (long)VA(int); 899 lnum = VA(size_t); 901 lnum = VA(unsigned long); 903 lnum = (unsigned long)(unsigned short)VA(int); 905 lnum = (unsigned long)VA(unsigne [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 912 CCValAssign &VA = ArgLocs[i]; local 923 VA.getLocMemOffset(), 929 } else if (VA.isRegLoc()) { 930 MVT RegVT = VA.getLocVT(); 932 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 935 } else { // VA.isRegLoc() 936 assert(VA.isMemLoc()); 938 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 939 VA.getLocMemOffset(), true); 942 ArgValue = DAG.getLoad(VA 1038 CCValAssign &VA = RVLocs[i]; local 1158 CCValAssign &VA = ArgLocs[i]; local 1355 CCValAssign VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 322 CCValAssign &VA = RVLocs[i]; local 324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 328 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 434 CCValAssign &VA = ArgLocs[i]; local 435 if (VA.isMemLoc()) { 458 CCValAssign &VA = ArgLocs[i]; local 463 switch (VA.getLocInfo()) { 470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA 843 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 959 CCValAssign &VA = ArgLocs[i]; local 963 switch (VA.getLocInfo()) { 967 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 970 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 973 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 979 if (VA.isRegLoc()) { 980 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 982 assert(VA.isMemLoc()); 984 int Offset = VA.getLocMemOffset(); 1133 CCValAssign &VA local 1260 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1916 CCValAssign &VA = ArgLocs[i]; local 1917 MVT ArgVT = ArgVTs[VA.getValNo()]; 1924 if (VA.isRegLoc() && !VA.needsCustom()) { 1926 } else if (VA.needsCustom()) { 1928 if (VA.getLocVT() != MVT::f64 || 1930 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1966 CCValAssign &VA = ArgLocs[i]; local 1967 unsigned Arg = ArgRegs[VA.getValNo()]; 1968 MVT ArgVT = ArgVTs[VA [all...] |
H A D | ARMISelLowering.h | 418 CCValAssign &VA, CCValAssign &NextVA, 422 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 430 const CCValAssign &VA,
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H A D | ARMISelLowering.cpp | 1245 CCValAssign VA = RVLocs[i]; local 1248 if (VA.needsCustom()) { 1250 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1254 VA = RVLocs[++i]; // skip ahead to next loc 1255 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1261 if (VA.getLocVT() == MVT::v2f64) { 1266 VA = RVLocs[++i]; // skip ahead to next loc 1267 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1270 VA = RVLocs[++i]; // skip ahead to next loc 1271 Hi = DAG.getCopyFromReg(Chain, dl, VA 1301 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 1314 PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVector<SDValue, 8> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 1406 CCValAssign &VA = ArgLocs[i]; local 1893 CCValAssign &VA = ArgLocs[i]; local 1963 CCValAssign &VA = RVLocs[i]; local 2545 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, DebugLoc dl) const argument 2692 CCValAssign &VA = ArgLocs[i]; local [all...] |
/external/clang/lib/Analysis/ |
H A D | LiveVariables.cpp | 308 for (const VariableArrayType* VA = FindVA(VD->getType()); 309 VA != 0; VA = FindVA(VA->getElementType())) { 310 AddLiveStmt(val.liveStmts, LV.SSetFact, VA->getSizeExpr());
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H A D | CFG.cpp | 1693 for (const VariableArrayType* VA = FindVA(VD->getType().getTypePtr()); 1694 VA != 0; VA = FindVA(VA->getElementType().getTypePtr())) { 1695 if (CFGBlock *newBlock = addStmt(VA->getSizeExpr())) 2562 for (const VariableArrayType *VA =FindVA(E->getArgumentType().getTypePtr()); 2563 VA != 0; VA = FindVA(VA->getElementType().getTypePtr())) 2564 lastBlock = addStmt(VA [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2645 CCValAssign &VA = ArgLocs[i]; local 2646 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2663 switch (VA.getLocInfo()) { 2666 if (VA.isRegLoc()) { 2678 unsigned LocRegLo = VA.getLocReg(); 2699 if (VA.isRegLoc()) { 2700 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2705 assert(VA.isMemLoc()); 2709 MemOpChains.push_back(passArgOnStack(StackPtr, VA 2852 CCValAssign &VA = ArgLocs[i]; local 3010 CCValAssign &VA = RVLocs[i]; local [all...] |
/external/icu4c/ |
H A D | runConfigureICU | 44 Linux/VA Use the IBM Visual Age compiler on Power PC Linux 219 Linux/VA)
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/external/llvm/lib/Target/R600/ |
H A D | SIISelLowering.cpp | 159 CCValAssign &VA = ArgLocs[ArgIdx++]; local 160 assert(VA.isRegLoc() && "Parameter must be in a register!"); 162 unsigned Reg = VA.getLocReg(); 163 MVT VT = VA.getLocVT();
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1925 CCValAssign &VA = ArgLocs[i]; local 1928 if (VA.isRegLoc()) { 1930 EVT ValVT = VA.getValVT(); 1953 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1959 assert(VA.isMemLoc()); 1961 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1962 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1967 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 3289 CCValAssign &VA = RVLocs[i]; local 3290 assert(VA 3567 CCValAssign &VA = ArgLocs[i]; local 4430 CCValAssign &VA = RVLocs[i]; local [all...] |