/external/clang/test/SemaTemplate/ |
H A D | value-dependent-null-pointer-constant.cpp | 5 const char *f0(bool Cond) { argument 6 return Cond? "honk" : N; 9 const char *f1(bool Cond) { argument 10 return Cond? N : "honk";
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H A D | overload-candidates.cpp | 52 template<typename Cond, typename T = void> struct enable_if : boost::enable_if<Cond::value, T> {};
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H A D | instantiate-expr-2.cpp | 77 struct Cond { 81 enum { resultT = Cond<true>::is, 82 resultF = Cond<false>::is }; 92 struct Cond { struct in namespace:N6 97 typedef Cond<true, int, char>::True True; 98 typedef Cond<true, int, char>::False False; 112 struct Cond { struct in namespace:N7 117 //Cond<true, int*, double> C; // Errors 119 //typedef Cond<true, int*, double>::Type Type; // Errors 120 typedef Cond<tru [all...] |
H A D | constructor-template.cpp | 60 X2 test(bool Cond, X2 x2) { argument 61 if (Cond) 80 X4 test_X4(bool Cond, X4 x4) { argument
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 118 SmallVectorImpl<MachineOperand> &Cond, 146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); 147 Cond.push_back(LastInst->getOperand(0)); 165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); 166 Cond.push_back(SecondLastInst->getOperand(0)); 189 const SmallVectorImpl<MachineOperand> &Cond, 193 assert((Cond.size() == 2 || Cond.size() == 0) && 197 if (!Cond.empty()) 198 Opc = (unsigned)Cond[ 115 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 187 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 79 SmallVectorImpl<MachineOperand> &Cond) const { 86 Cond.push_back(MachineOperand::CreateImm(Opc)); 89 Cond.push_back(Inst->getOperand(i)); 95 SmallVectorImpl<MachineOperand> &Cond, 98 BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); 105 const SmallVectorImpl<MachineOperand>& Cond) 107 unsigned Opc = Cond[0].getImm(); 111 for (unsigned i = 1; i < Cond.size(); ++i) { 112 if (Cond[i].isReg()) 113 MIB.addReg(Cond[ 92 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 123 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument 190 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, SmallVectorImpl<MachineInstr*> &BranchInstrs) const argument [all...] |
H A D | MipsInstrInfo.h | 50 SmallVectorImpl<MachineOperand> &Cond, 57 const SmallVectorImpl<MachineOperand> &Cond, 61 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 65 SmallVectorImpl<MachineOperand> &Cond, 100 SmallVectorImpl<MachineOperand> &Cond) const; 103 const SmallVectorImpl<MachineOperand>& Cond) const;
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | ConstraintManager.h | 68 DefinedSVal Cond, 75 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { argument 76 ProgramStateRef StTrue = assume(State, Cond, true); 78 // If StTrue is infeasible, asserting the falseness of Cond is unnecessary 86 assert(assume(State, Cond, false) && "System is over constrained."); 91 ProgramStateRef StFalse = assume(State, Cond, false);
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | SimpleConstraintManager.h | 36 ProgramStateRef assume(ProgramStateRef state, DefinedSVal Cond, 39 ProgramStateRef assume(ProgramStateRef state, Loc Cond, bool Assumption); 41 ProgramStateRef assume(ProgramStateRef state, NonLoc Cond, bool Assumption); 89 Loc Cond, 93 NonLoc Cond,
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H A D | SimpleConstraintManager.cpp | 59 DefinedSVal Cond, 61 if (Optional<NonLoc> NV = Cond.getAs<NonLoc>()) 63 return assume(state, Cond.castAs<Loc>(), Assumption); 75 Loc Cond, bool Assumption) { 76 switch (Cond.getSubKind()) { 84 const MemRegion *R = Cond.castAs<loc::MemRegionVal>().getRegion(); 106 bool b = Cond.castAs<loc::ConcreteInt>().getValue() != 0; 156 NonLoc Cond, 161 if (!canReasonAbout(Cond)) { 163 SymbolRef sym = Cond 58 assume(ProgramStateRef state, DefinedSVal Cond, bool Assumption) argument 74 assumeAux(ProgramStateRef state, Loc Cond, bool Assumption) argument 155 assumeAux(ProgramStateRef state, NonLoc Cond, bool Assumption) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreInstrInfo.cpp | 189 SmallVectorImpl<MachineOperand> &Cond, 222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 223 Cond.push_back(LastInst->getOperand(0)); 244 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 245 Cond.push_back(SecondLastInst->getOperand(0)); 277 const SmallVectorImpl<MachineOperand> &Cond, 281 assert((Cond.size() == 2 || Cond.size() == 0) && 285 if (Cond.empty()) { 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[ 187 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 275 InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | XCoreInstrInfo.h | 54 SmallVectorImpl<MachineOperand> &Cond, 59 const SmallVectorImpl<MachineOperand> &Cond, 88 SmallVectorImpl<MachineOperand> &Cond) const;
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/external/clang/test/SemaCXX/ |
H A D | vector.cpp | 40 void conditional(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, argument 43 __typeof__(Cond? c16 : c16) *c16p1 = &c16; 44 __typeof__(Cond? ll16 : ll16) *ll16p1 = &ll16; 45 __typeof__(Cond? c16e : c16e) *c16ep1 = &c16e; 46 __typeof__(Cond? ll16e : ll16e) *ll16ep1 = &ll16e; 49 __typeof__(Cond? c16 : c16e) *c16ep2 = &c16e; 50 __typeof__(Cond? c16e : c16) *c16ep3 = &c16e; 51 __typeof__(Cond? ll16 : ll16e) *ll16ep2 = &ll16e; 52 __typeof__(Cond? ll16e : ll16) *ll16ep3 = &ll16e; 55 (void)(Cond 108 test_implicit_conversions(bool Cond, char16 c16, longlong16 ll16, char16_e c16e, longlong16_e ll16e, convertible_to<char16> to_c16, convertible_to<longlong16> to_ll16, convertible_to<char16_e> to_c16e, convertible_to<longlong16_e> to_ll16e, convertible_to<char16&> rto_c16, convertible_to<char16_e&> rto_c16e) argument [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.h | 74 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 78 SmallVectorImpl<MachineOperand> &Cond, 84 const SmallVectorImpl<MachineOperand> &Cond,
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H A D | MSP430InstrInfo.cpp | 127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 128 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); 130 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); 154 Cond[0].setImm(CC); 172 SmallVectorImpl<MachineOperand> &Cond, 207 Cond.clear(); 231 if (Cond.empty()) { 234 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 240 assert(Cond.size() == 1); 248 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[ 169 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 260 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | MSP430BranchSelector.cpp | 150 SmallVector<MachineOperand, 1> Cond; local 151 Cond.push_back(I->getOperand(1)); 154 TII->ReverseBranchCondition(Cond); 156 .addImm(4).addOperand(Cond[0]);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 182 SmallVectorImpl<MachineOperand> &Cond, 200 Cond.push_back(LastInst->getOperand(0)); 219 Cond.push_back(SecondLastInst->getOperand(0)); 264 const SmallVectorImpl<MachineOperand> &Cond, 268 assert((Cond.size() == 1 || Cond.size() == 0) && 273 if (Cond.empty()) // Unconditional branch 277 .addReg(Cond[0].getReg()).addMBB(TBB); 283 .addReg(Cond[0].getReg()).addMBB(TBB); 179 AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 262 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument
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H A D | NVPTXInstrInfo.h | 68 SmallVectorImpl<MachineOperand> &Cond, 73 const SmallVectorImpl<MachineOperand> &Cond,
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 210 SmallVectorImpl<MachineOperand> &Cond, 242 Cond.push_back(LastInst->getOperand(0)); 243 Cond.push_back(LastInst->getOperand(1)); 252 Cond.push_back(MachineOperand::CreateImm(1)); 253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 263 Cond.push_back(MachineOperand::CreateImm(0)); 264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, 288 Cond.push_back(SecondLastInst->getOperand(0)); 289 Cond.push_back(SecondLastInst->getOperand(1)); 301 Cond 208 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 371 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | PPCInstrInfo.h | 116 SmallVectorImpl<MachineOperand> &Cond, 121 const SmallVectorImpl<MachineOperand> &Cond, 147 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.h | 75 SmallVectorImpl<MachineOperand> &Cond, 82 const SmallVectorImpl<MachineOperand> &Cond,
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 140 /// setting TBB to the destination basic block and populating the Cond vector 145 SmallVectorImpl<MachineOperand> &Cond) { 154 Cond.push_back(MachineOperand::CreateImm(I->getOpcode())); 155 Cond.push_back(I->getOperand(0)); 163 Cond.push_back(MachineOperand::CreateImm(I->getOpcode())); 164 Cond.push_back(I->getOperand(0)); 165 Cond.push_back(I->getOperand(1)); 177 SmallVectorImpl<MachineOperand> &Cond, 203 classifyCondBranch(LastInst, TBB, Cond); 239 Cond 144 classifyCondBranch(MachineInstr *I, MachineBasicBlock *&TBB, SmallVectorImpl<MachineOperand> &Cond) argument 175 AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const argument 304 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const argument [all...] |
H A D | AArch64InstrInfo.h | 63 SmallVectorImpl<MachineOperand> &Cond, 67 const SmallVectorImpl<MachineOperand> &Cond, 70 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1068 ISD::CondCode Cond, bool foldBooleans, 1073 switch (Cond) { 1084 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1097 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1099 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1102 Cond = ISD::SETNE; 1106 Cond = ISD::SETEQ; 1110 Zero, Cond); 1127 if ((Cond 1067 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, DebugLoc dl) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 775 inline bool isTrueWhenEqual(CondCode Cond) { argument 776 return ((int)Cond & 1) != 0; 783 inline unsigned getUnorderedFlavor(CondCode Cond) { argument 784 return ((int)Cond >> 3) & 3;
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