| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 1703a714954f9ef0c32415423e2a1e15b152e711 |
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15-Nov-2013 |
Reed Kotler <rkotler@mips.com> |
Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| b359bda93d410623bbbc96dc9968d94447169a79 |
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08-Oct-2013 |
Reed Kotler <rkotler@mips.com> |
Let rotr and bswap be handled by expansion for Mips16 since we don't
have native instructions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 6ff59a16a05d43fdda587ce600b5b42a63cf3d33 |
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28-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.
Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:
1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25 // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25 // jump to lazy-binding stub again.
With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:
1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25 // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25 // directly jump to func.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 200a7434f6abc1e469fdf1ee547bc3fe4fbfcc02 |
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27-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rewrite MipsTargetLowering::getAddr functions as template functions.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| e36a62c23d332658e4513d67eedb392b9c27f470 |
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25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert r191350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 793803449870a661c1a09e400df9b04492772196 |
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25-Sep-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define getTargetNode as a template function.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 1e07de352947aaf2f9137113cc594d8204da2b77 |
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09-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Add another intrinsic that LLVM gives an incorrect prototype to.
I need to go through all the runtime routine list and see if there
are any more I need to add for mips16 floating point. Prototypes must
be correct or else I don't know to add a helper function call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 1858786285139b87961d9ca08de91dcd59364afb |
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07-Aug-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| b1fa7d4d26533bdd021c3269d14c30eb6096fb7a |
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01-Aug-2013 |
Reed Kotler <rkotler@mips.com> |
Fix some issues with Mips16 floating when certain intrinsics are present.
This is actually an LLVM bug in the way it generates signatures for these
when soft float is enabled. For example, floor ends up having the signature
of int64(int64). The signature part is not the same as where the actual
parameter types are recorded, and those ARE of course int64(int64) when
soft float is enabled. (Yes, Mips16 hard float uses soft float but with
different runtime rounes but then has to interoperate with Mips32 using
normal floating point). This logic will eventually be moved to the
Mips16HardFloat pass so it's not worth sorting out these issues in LLVM
since nobody but Mips16 cares about these signatures, as far as I know,
and even I won't eventually either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 90cd06e90be1db06bc4812ae9ec96b6638847285 |
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13-Jun-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Mips: Remove global set.
Backends shouldn't retain any global state. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| b0ee97a366a07c05b2c8ab314e29f5e72a9b7bfb |
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10-Jun-2013 |
Reed Kotler <rkotler@mips.com> |
Fix a regression I introduced when I expanded the complex pseudos in
the Mips16 port. A few of the psuedos could either take signed
or unsigned arguments and I did not distinguish the case and improperly
rejected some valid cases that the assembler had previously accepted
when they were pure pseudos that expanded as assembly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| bf00bf9ad2f07c5c06986930842ace28b8fb2518 |
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21-May-2013 |
Reed Kotler <rkotler@mips.com> |
Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.
As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 46090914b783b632618268f2a5c99aab83732688 |
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11-May-2013 |
Reed Kotler <rkotler@mips.com> |
Checkin in of first of several patches to finish implementation of
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| b109ea8245e2948ea6d06a6e6cbab7c6788da211 |
|
22-Apr-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| 6265d5c91a18b2fb6499eb581c488315880c044d |
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20-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
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| f8b0a08b6a2e2f4eacdb05eae9a8dd704b692b55 |
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14-Mar-2013 |
Reed Kotler <rkotler@mips.com> |
Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup.
Normally you need to add register classes and then call
computeRegisterProperties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
|
| 5ac065a79767cc112eba63136183b7103765d0d3 |
|
13-Mar-2013 |
Akira Hatanaka <ahatanaka@mips.com> |
[mips] Define two subclasses of MipsTargetLowering. Mips16TargetLowering is for
mips16 and MipsSETargetLowering is for mips32/64.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/Mips16ISelLowering.cpp
|