| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSplitTFRCondSets.cpp | 100 int SrcReg2 = MI->getOperand(3).getReg(); local
118 if (DestReg != SrcReg2) {
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
157 int SrcReg2 = MI->getOperand(3).getReg(); local
173 if (DestReg != SrcReg2) {
176 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
|
| H A D | HexagonInstrInfo.cpp | 339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
343 unsigned &SrcReg, unsigned &SrcReg2,
397 SrcReg2 = MI->getOperand(2).getReg();
407 SrcReg2 = 0;
342 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
|
| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 382 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ? local
387 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
413 // Clear any intervening kills of SrcReg and SrcReg2.
417 if (SrcReg2)
418 MBBI->clearRegisterKills(SrcReg2, TRI);
|
| H A D | SystemZInstrInfo.cpp | 400 unsigned &SrcReg, unsigned &SrcReg2,
408 SrcReg2 = 0;
484 unsigned SrcReg, unsigned SrcReg2,
487 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
399 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
483 optimizeCompareInstr(MachineInstr *Compare, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
|
| /external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 417 unsigned SrcReg, SrcReg2; local
419 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
421 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
425 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 610 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
613 unsigned &SrcReg2, int &CmpMask,
632 SrcReg2 = MI->getOperand(2).getReg();
641 SrcReg2 = 0;
650 SrcReg2 = 0;
703 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
741 if (CmpValue != 0 || SrcReg2 != 0)
612 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
702 optimizeCompareInstr( MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
|
| H A D | AArch64FastISel.cpp | 952 unsigned SrcReg2; local
954 SrcReg2 = getRegForValue(Src2Value);
955 if (SrcReg2 == 0)
965 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
966 if (SrcReg2 == 0)
982 .addReg(SrcReg2);
990 .addReg(SrcReg2);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2)
95 fpi->U.I.SrcReg[2] = SrcReg2;
78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 778 /// in SrcReg and SrcReg2 if having two register operands, and the value it
782 unsigned &SrcReg, unsigned &SrcReg2,
791 unsigned SrcReg, unsigned SrcReg2,
781 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
790 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2)
95 fpi->U.I.SrcReg[2] = SrcReg2;
78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 796 unsigned SrcReg2 = 0; local
798 SrcReg2 = getRegForValue(SrcValue2);
799 if (SrcReg2 == 0)
811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
813 SrcReg2 = ExtReg;
819 .addReg(SrcReg1).addReg(SrcReg2);
1179 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); local
1180 if (SrcReg2 == 0) return false;
1184 std::swap(SrcReg1, SrcReg2);
1187 .addReg(SrcReg1).addReg(SrcReg2);
[all...] |
| H A D | PPCInstrInfo.cpp | 1282 unsigned &SrcReg, unsigned &SrcReg2,
1293 SrcReg2 = 0;
1304 SrcReg2 = MI->getOperand(2).getReg();
1310 unsigned SrcReg, unsigned SrcReg2,
1411 if (SrcReg2 != 0)
1450 Instr.getOperand(2).getReg() == SrcReg2) ||
1451 (Instr.getOperand(1).getReg() == SrcReg2 &&
1497 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1281 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
1309 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1438 unsigned SrcReg2 = 0; local
1440 SrcReg2 = getRegForValue(Src2Value);
1441 if (SrcReg2 == 0) return false;
1449 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1450 if (SrcReg2 == 0) return false;
1457 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1459 .addReg(SrcReg1).addReg(SrcReg2));
1777 unsigned SrcReg2 local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 2137 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2141 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, argument
2148 SrcReg2 = 0;
2155 SrcReg2 = MI->getOperand(1).getReg();
2162 SrcReg2 = 0;
2225 unsigned SrcReg2, int ImmValue,
2232 OI->getOperand(2).getReg() == SrcReg2) ||
2233 (OI->getOperand(1).getReg() == SrcReg2 &&
2255 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, argument
2293 if (SrcReg2 !
2224 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2251 unsigned SrcReg2; local
2254 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2264 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2271 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
3354 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, argument
3366 SrcReg2 = 0;
3376 SrcReg2 = 0;
3385 SrcReg2 = MI->getOperand(2).getReg();
3397 SrcReg2 = 0;
3406 SrcReg2
3431 isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
3580 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |