/external/llvm/lib/Target/R600/ |
H A D | SIInsertWaits.cpp | 75 Counters getHwCounts(MachineInstr &MI); 84 void pushInstruction(MachineInstr &MI); 92 bool unorderedDefines(MachineInstr &MI); 95 Counters handleOperands(MachineInstr &MI); 123 Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { argument 125 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; 132 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); 137 if (TII->isSMRD(MI.getOpcode())) { 139 MachineOperand &Op = MI 204 pushInstruction(MachineInstr &MI) argument 313 handleOperands(MachineInstr &MI) argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMConstantIslandPass.cpp | 185 MachineInstr *MI; member in struct:__anon25967::ARMConstantIslands::CPUser 196 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm), 200 /// getMaxDisp - Returns the maximum displacement supported by MI. 235 MachineInstr *MI; member in struct:__anon25967::ARMConstantIslands::ImmBranch 240 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {} 282 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI); 294 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, 299 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp); 304 bool mayOptimizeThumb2Instruction(const MachineInstr *MI) const; 313 unsigned getOffsetOf(MachineInstr *MI) cons 873 splitBlockBeforeInstr(MachineInstr *MI) argument 1033 isCPEntryInRange(MachineInstr *MI, unsigned UserOffset, MachineInstr *CPEMI, unsigned MaxDisp, bool NegOk, bool DoDump) argument 1317 MachineBasicBlock::iterator MI = UserMI; local 1505 isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB, unsigned MaxDisp) argument 1531 MachineInstr *MI = Br.MI; local 1549 MachineInstr *MI = Br.MI; local 1572 MachineInstr *MI = Br.MI; local 1659 MachineInstr *MI = PushPopMIs[i]; local 1852 MachineInstr *MI = T2JumpTables[i]; local [all...] |
H A D | ARMBaseRegisterInfo.cpp | 444 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { argument 445 const MCInstrDesc &Desc = MI->getDesc(); 454 InstrOffs = MI->getOperand(Idx+1).getImm(); 459 const MachineOperand &OffOp = MI->getOperand(Idx+1); 468 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 469 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 475 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 476 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 482 InstrOffs = MI->getOperand(ImmIdx).getImm(); 498 needsFrameBaseReg(MachineInstr *MI, int64_ argument 605 resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const argument 633 isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const argument 705 MachineInstr &MI = *II; local [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.h | 47 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 49 bool isAsCheapAsAMove(const MachineInstr *MI) const override; 51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 54 unsigned isLoadFromStackSlot(const MachineInstr *MI, 56 unsigned isStoreToStackSlot(const MachineInstr *MI, 61 bool hasShiftedReg(const MachineInstr *MI) const; 65 bool hasExtendedReg(const MachineInstr *MI) const; 68 bool isGPRZero(const MachineInstr *MI) const; 71 bool isGPRCopy(const MachineInstr *MI) const; 74 bool isFPRCopy(const MachineInstr *MI) cons [all...] |
H A D | AArch64A57FPLoadBalancing.cpp | 70 static bool isMul(MachineInstr *MI) { argument 71 switch (MI->getOpcode()) { 83 static bool isMla(MachineInstr *MI) { argument 84 switch (MI->getOpcode()) { 136 void scanInstruction(MachineInstr *MI, unsigned Idx, 189 Chain(MachineInstr *MI, unsigned Idx, Color C) argument 190 : StartInst(MI), LastInst(MI), KillInst(nullptr), 193 Insts.insert(MI); 198 void add(MachineInstr *MI, unsigne argument 210 contains(MachineInstr *MI) argument 219 setKill(MachineInstr *MI, unsigned Idx, bool Immutable) argument 576 scanInstruction(MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain*> &ActiveChains, std::set<std::unique_ptr<Chain>> &AllChains) argument 660 MachineInstr *MI = MO.getParent(); local [all...] |
/external/llvm/lib/Target/NVPTX/InstPrinter/ |
H A D | NVPTXInstPrinter.cpp | 74 void NVPTXInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 76 printInstruction(MI, OS); 82 void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 84 const MCOperand &Op = MI->getOperand(OpNo); 96 void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O, argument 98 const MCOperand &MO = MI->getOperand(OpNum); 146 void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O, argument 148 const MCOperand &MO = MI->getOperand(OpNum); 219 void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum, argument 222 const MCOperand &MO = MI 267 printMemOperand(const MCInst *MI, int OpNum, raw_ostream &O, const char *Modifier) argument 283 printProtoIdent(const MCInst *MI, int OpNum, raw_ostream &O, const char *Modifier) argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 77 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, argument 80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); 81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); 85 SC = resolveSchedClass(MI); 89 return MI->isTransient() ? 0 : 1; 103 resolveSchedClass(const MachineInstr *MI) const { 106 unsigned SchedClass = MI->getDesc().getSchedClass(); 117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); 128 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) { argument 131 const MachineOperand &MO = MI 144 findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) argument 229 computeInstrLatency(const MachineInstr *MI, bool UseDefaultDefLatency) const argument [all...] |
H A D | LiveRangeEdit.cpp | 149 MachineBasicBlock::iterator MI, 155 TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri); 157 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late) 172 MachineInstr *MI = MO.getParent(); local 174 if (DefMI && DefMI != MI) 176 if (!MI->canFoldAsLoad()) 178 DefMI = MI; 180 if (UseMI && UseMI != MI) 185 UseMI = MI; 224 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSe argument 148 rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &tri, bool Late) argument 234 DEBUG(dbgs() << "Won't delete: " << Idx << '\\t' << *MI); local 241 DEBUG(dbgs() << "Can't delete: " << Idx << '\\t' << *MI); local 245 DEBUG(dbgs() << "Deleting dead def " << Idx << '\\t' << *MI); local [all...] |
H A D | MachineCopyPropagation.cpp | 56 void removeCopy(MachineInstr *MI); 87 const MachineInstr *MI) { 89 if (MI->getParent() != MBB) 93 MachineBasicBlock::const_iterator E2 = MI; 130 // Remove MI from the function because it has been determined it is dead. 133 void MachineCopyPropagation::removeCopy(MachineInstr *MI) { argument 134 MI->setDesc(TII->get(TargetOpcode::KILL)); 147 MachineInstr *MI = &*I; local 150 if (MI->isCopy()) { 151 unsigned Def = MI 86 NoInterveningSideEffect(const MachineInstr *CopyMI, const MachineInstr *MI) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 118 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const; 119 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const; 120 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode, 122 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode, 124 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode, 126 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode, 137 unsigned isLoadFromStackSlot(const MachineInstr *MI, 139 unsigned isStoreToStackSlot(const MachineInstr *MI, 141 bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 152 bool analyzeCompare(const MachineInstr *MI, unsigne [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 54 MachineInstr * MI, MachineBasicBlock * BB) const 58 MachineBasicBlock::iterator I = *MI; 60 switch (MI->getOpcode()) { 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 66 .addOperand(MI->getOperand(0)) 67 .addOperand(MI->getOperand(1)) 77 .addOperand(MI->getOperand(0)) 78 .addOperand(MI->getOperand(1)) 89 .addOperand(MI->getOperand(0)) 90 .addOperand(MI 53 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument [all...] |
H A D | AMDGPUAsmPrinter.h | 38 virtual void EmitInstruction(const MachineInstr *MI);
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 54 MachineInstr * MI, MachineBasicBlock * BB) const 58 MachineBasicBlock::iterator I = *MI; 60 switch (MI->getOpcode()) { 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 66 .addOperand(MI->getOperand(0)) 67 .addOperand(MI->getOperand(1)) 77 .addOperand(MI->getOperand(0)) 78 .addOperand(MI->getOperand(1)) 89 .addOperand(MI->getOperand(0)) 90 .addOperand(MI 53 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument [all...] |
H A D | AMDGPUAsmPrinter.h | 38 virtual void EmitInstruction(const MachineInstr *MI);
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/external/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 316 static bool isFPCopy(MachineInstr *MI) { 317 unsigned DstReg = MI->getOperand(0).getReg(); 318 unsigned SrcReg = MI->getOperand(1).getReg(); 417 MachineInstr *MI = I; 418 uint64_t Flags = MI->getDesc().TSFlags; 421 if (MI->isInlineAsm()) 424 if (MI->isCopy() && isFPCopy(MI)) 427 if (MI->isImplicitDef() && 428 X86::RFP80RegClass.contains(MI [all...] |
H A D | X86AsmPrinter.cpp | 174 static void printOperand(X86AsmPrinter &P, const MachineInstr *MI, 181 static void printPCRelImm(X86AsmPrinter &P, const MachineInstr *MI, argument 183 const MachineOperand &MO = MI->getOperand(OpNo); 188 printOperand(P, MI, OpNo, O); 199 static void printOperand(X86AsmPrinter &P, const MachineInstr *MI, argument 202 const MachineOperand &MO = MI->getOperand(OpNo); 232 static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, argument 235 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 236 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 237 const MachineOperand &DispSpec = MI 284 printMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr) argument 296 printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr, unsigned AsmVariant = 1) argument 379 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 470 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
H A D | X86CodeEmitter.cpp | 67 const MachineInstr &MI, 71 const MachineInstr &MI, 76 const MachineInstr &MI) const; 78 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 105 void emitMemModRMByte(const MachineInstr &MI, 114 unsigned char getVEXRegisterEncoding(const MachineInstr &MI, 163 static unsigned determineREX(const MachineInstr &MI) { argument 165 const MCInstrDesc &Desc = MI.getDesc(); 181 const MachineOperand& MO = MI.getOperand(i); 191 if (X86InstrInfo::isX86_64ExtendedReg(MI [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 38 MachineBasicBlock::iterator MI, 43 if (MI != MBB.end()) DL = MI->getDebugLoc(); 54 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) 58 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) 66 MachineBasicBlock::iterator MI, 71 if (MI != MBB.end()) DL = MI->getDebugLoc(); 82 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) 85 BuildMI(MBB, MI, D 37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 65 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | MSP430InstrInfo.h | 61 MachineBasicBlock::iterator MI, 67 MachineBasicBlock::iterator MI, 72 unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 77 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
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/external/chromium_org/third_party/libjingle/source/talk/session/media/ |
H A D | mediamonitor.h | 66 template<class MC, class MI> 73 sigslot::signal2<MC*, const MI&> SignalUpdate; 82 MI stats(media_info_); 90 MI media_info_;
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/external/llvm/include/llvm/CodeGen/ |
H A D | StackMapLivenessAnalysis.h | 55 void addLiveOutSetToMI(MachineInstr &MI);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXFrameLowering.cpp | 50 MachineInstr *MI = local 54 BuildMI(MBB, MI, dl, 59 MachineInstr *MI = local 63 BuildMI(MBB, MI, dl,
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H A D | NVPTXInstrInfo.cpp | 68 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, argument 74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift; 78 MachineOperand dest = MI.getOperand(0); 79 MachineOperand src = MI.getOperand(1); 91 bool NVPTXInstrInfo::isReadSpecialReg(MachineInstr &MI) const { 92 switch (MI.getOpcode()) { 112 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI, argument 116 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift; 119 AddrSpace = getLdStCodeAddrSpace(MI); 123 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI, argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 73 HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI, argument 77 switch(MI->getOpcode()) { 98 MI->setDesc(QII->get(NewOpcode)); 99 MI->getOperand(1).setMBB(NewTarget); 113 MachineInstr *MI = MII; local 114 int Opc = MI->getOpcode(); 166 if ((MI->getOpcode() == Hexagon::JMP_t) || 167 (MI->getOpcode() == Hexagon::JMP_f)) { 168 CondBranchTarget = MI->getOperand(1).getMBB(); 191 InvertAndChangeJumpTarget(MI, UncondTarge [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSERegisterInfo.cpp | 109 MachineInstr &MI = *II; local 110 MachineFunction &MF = *MI.getParent()->getParent(); 150 Offset += MI.getOperand(OpNo + 1).getImm(); 154 if (!MI.isDebugValue()) { 158 unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode()); 159 unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode()); 166 MachineBasicBlock &MBB = *MI.getParent(); 184 MachineBasicBlock &MBB = *MI.getParent(); 202 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); 203 MI [all...] |