/external/llvm/lib/Target/ |
H A D | TargetMachineC.cpp | 185 TargetMachine* TM = unwrap(T); local 192 const DataLayout* td = TM->getDataLayout(); 211 if (TM->addPassesToEmitFile(pass, OS, ft)) {
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/external/llvm/lib/Target/X86/ |
H A D | X86Subtarget.h | 244 const std::string &FS, X86TargetMachine &TM, 431 const TargetMachine &TM)const; 440 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
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H A D | X86CodeEmitter.cpp | 47 X86TargetMachine &TM; member in class:__anon26186::Emitter 56 : MachineFunctionPass(ID), II(nullptr), TD(nullptr), TM(tm), 58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 110 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 124 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, argument 126 return new Emitter<JITCodeEmitter>(TM, JCE); 134 II = TM.getInstrInfo(); 135 TD = TM.getDataLayout(); 136 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit(); 137 IsPIC = TM [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineInstr.cpp | 260 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 263 if (!TM) 267 TM = &MF->getTarget(); 268 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr; 1459 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM, argument 1466 if (!TM && MF) 1467 TM = &MF->getTarget(); 1482 getOperand(StartOp).print(OS, TM); 1492 if (TM [all...] |
H A D | MachineRegisterInfo.cpp | 25 MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM) argument 26 : TM(TM), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true) { 69 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument 70 const TargetInstrInfo *TII = TM.getInstrInfo();
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H A D | SjLjEHPrepare.cpp | 47 const TargetMachine *TM; member in class:__anon25821::SjLjEHPrepare 63 explicit SjLjEHPrepare(const TargetMachine *TM) : FunctionPass(ID), TM(TM) {} argument 85 FunctionPass *llvm::createSjLjEHPreparePass(const TargetMachine *TM) { argument 86 return new SjLjEHPrepare(TM); 193 const TargetLowering *TLI = TM->getTargetLowering();
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H A D | MachineInstrBundle.cpp | 106 const TargetMachine &TM = MBB.getParent()->getTarget(); local 107 const TargetInstrInfo *TII = TM.getInstrInfo(); 108 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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H A D | GCStrategy.cpp | 68 const TargetMachine *TM; member in class:__anon25748::GCMachineCodeAnalysis 380 const TargetFrameLowering *TFI = TM->getFrameLowering(); 404 TM = &MF.getTarget(); 406 TII = TM->getInstrInfo();
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H A D | StackProtector.cpp | 52 FunctionPass *llvm::createStackProtectorPass(const TargetMachine *TM) { argument 53 return new StackProtector(TM); 88 TLI = TM->getTargetLowering(); 375 EnableSelectionDAGSP && !TM->Options.EnableFastISel;
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H A D | VirtRegMap.cpp | 158 const TargetMachine *TM; member in class:__anon25833::VirtRegRewriter 207 TM = &MF->getTarget(); 208 TRI = TM->getRegisterInfo(); 209 TII = TM->getInstrInfo();
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 54 AArch64AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 55 : AsmPrinter(TM, Streamer), 56 Subtarget(&TM.getSubtarget<AArch64Subtarget>()), 148 const DataLayout *TD = TM.getDataLayout(); 256 static_cast<const AArch64RegisterInfo *>(TM.getRegisterInfo());
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/external/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 41 const TargetMachine &TM; member in class:__anon26050::final 57 TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()), 58 TLI(*TM.getTargetLowering()), 59 Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
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H A D | Mips16InstrInfo.h | 26 explicit Mips16InstrInfo(MipsTargetMachine &TM);
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H A D | MipsOs16.cpp | 143 ModulePass *llvm::createMipsOs16(MipsTargetMachine &TM) { argument
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H A D | MipsSEISelLowering.h | 23 explicit MipsSETargetLowering(MipsTargetMachine &TM);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 46 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 47 : AsmPrinter(TM, Streamer) {} 188 if (TM.getRelocationModel() != Reloc::PIC_) { 190 switch(TM.getCodeModel()) { 280 if (!TM.getSubtarget<SparcSubtarget>().is64Bit()) 299 const DataLayout *DL = TM.getDataLayout(); 453 unsigned PtrSize = TM.getDataLayout()->getPointerSize(0);
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/external/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 177 const TargetMachine &TM; member in class:llvm::CCState 241 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs, 249 const TargetMachine &getTarget() const { return TM; }
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/external/llvm/include/llvm/ExecutionEngine/ |
H A D | ExecutionEngine.h | 149 TargetMachine *TM); 155 TargetMachine *TM); 726 ExecutionEngine *create(TargetMachine *TM);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.h | 311 NVPTXAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 312 : AsmPrinter(TM, Streamer), 313 nvptxSubtarget(TM.getSubtarget<NVPTXSubtarget>()) {
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600InstrInfo.cpp | 30 TM(tm) 144 DFAPacketizer *R600InstrInfo::CreateTargetScheduleState(const TargetMachine *TM, argument 147 const InstrItineraryData *II = TM->getInstrItineraryData(); 148 return TM->getSubtarget<AMDGPUSubtarget>().createDFAPacketizer(II);
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H A D | R600RegisterInfo.cpp | 23 TM(tm),
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.h | 32 const TargetMachine *TM; member in class:llvm::InstrEmitter
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/external/llvm/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 79 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType()); 185 const DataLayout *DL = TM.getDataLayout(); 194 const DataLayout *DL = TM.getDataLayout(); 417 Reloc::Model RelocM = TM.getRelocationModel(); 437 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM)); 561 const DataLayout *TD = TM.getDataLayout(); 675 if (TM.getRelocationModel() == Reloc::PIC_) { 690 if (!TM.Options.UnsafeFPMath) { 696 if (TM.Options.NoInfsFPMath && TM [all...] |
H A D | ARMTargetTransformInfo.cpp | 37 const ARMBaseTargetMachine *TM; member in class:__anon25985::final 46 ARMTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) { 50 ARMTTI(const ARMBaseTargetMachine *TM) argument 51 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), 52 TLI(TM->getTargetLowering()) { 146 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) { argument 147 return new ARMTTI(TM);
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.h | 26 R600TargetLowering(TargetMachine &TM);
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