/external/llvm/lib/CodeGen/ |
H A D | RegAllocBase.cpp | 60 TRI = &vrm.getTargetRegInfo();
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H A D | TwoAddressInstructionPass.cpp | 73 const TargetRegisterInfo *TRI; member in class:__anon25830::TwoAddressInstructionPass 293 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); 494 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { argument 499 return TRI->regsOverlap(RegA, RegB); 547 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI); 548 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI); 614 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); 638 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) 1194 TRI->getAllocatableClass( 1195 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *M [all...] |
H A D | RegAllocBasic.cpp | 174 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 186 DEBUG(dbgs() << "spilling " << TRI->getName(PhysReg) <<
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H A D | TargetSchedule.cpp | 271 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 272 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
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H A D | BranchFolding.cpp | 146 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 191 TRI = tri; 197 if (MRI.tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF)) 391 BitVector RegsLiveAtExit(TRI->getNumRegs()); 393 for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++) 1491 const TargetRegisterInfo *TRI, 1506 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1516 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1574 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1578 for (MCSubRegIterator SubRegs(Reg, TRI); SubReg 1489 findHoistingInsertPosAndDeps(MachineBasicBlock *MBB, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, SmallSet<unsigned,4> &Uses, SmallSet<unsigned,4> &Defs) argument [all...] |
H A D | MachineCSE.cpp | 43 const TargetRegisterInfo *TRI; member in class:__anon25762::MachineCSE 141 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC, 143 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI); 187 if (!TRI->regsOverlap(MO.getReg(), Reg)) 226 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 255 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI) 667 TRI = MF.getTarget().getRegisterInfo();
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H A D | ScheduleDAGInstrs.cpp | 227 if (TRI->isPhysicalRegister(Reg)) 259 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 306 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 772 Defs.setUniverse(TRI->getNumRegs()); 773 Uses.setUniverse(TRI->getNumRegs()); 820 if (TRI->isPhysicalRegister(Reg)) 1066 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 1092 for (MCSubRegIterator SubRegs(SuperReg, TRI); SubRegs.isValid(); ++SubRegs) { 1108 LiveRegs.resize(TRI->getNumRegs()); 1109 BitVector killedRegs(TRI [all...] |
H A D | InlineSpiller.cpp | 70 const TargetRegisterInfo &TRI; member in class:__anon25751::InlineSpiller 155 TRI(*mf.getTarget().getRegisterInfo()), 745 MRI.getRegClass(SVI.SpillReg), &TRI); 909 TRI); 962 MI->addRegisterDead(Reg, &TRI); 1126 MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI); 1131 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units) { 1180 MRI.getRegClass(NewVReg), &TRI); 1196 MRI.getRegClass(NewVReg), &TRI);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.h | 34 const TargetRegisterInfo *TRI; member in class:llvm::InstrEmitter
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H A D | ScheduleDAGFast.cpp | 121 LiveRegDefs.resize(TRI->getNumRegs(), nullptr); 122 LiveRegCycles.resize(TRI->getNumRegs(), 0); 453 const TargetRegisterInfo *TRI) { 455 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { 481 RegAdded, LRegs, TRI); 505 CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI); 518 CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); 577 TRI->getMinimalPhysRegClass(Reg, VT); 578 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); 449 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument
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/external/llvm/lib/Target/ARM/ |
H A D | MLxExpansionPass.cpp | 52 const TargetRegisterInfo *TRI; member in struct:__anon26004::MLxExpansion 195 return MI->readsRegister(Reg, TRI); 291 TII->getRegClass(MCID1, 0, TRI, MF)); 382 TRI = Fn.getTarget().getRegisterInfo();
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H A D | ARMAsmPrinter.cpp | 139 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 140 Reg = TRI->getSubReg(Reg, ARM::gsub_0); 232 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 235 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) { 238 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; 264 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 265 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); 267 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); 320 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 321 unsigned Reg = TRI 346 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 361 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local [all...] |
/external/llvm/lib/Target/R600/ |
H A D | R600ControlFlowFinalizer.cpp | 220 const R600RegisterInfo *TRI; member in class:__anon26114::R600ControlFlowFinalizer 293 DstMI = TRI->getMatchingSuperReg(Reg, 294 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), 302 SrcMI = TRI->getMatchingSuperReg(Reg, 303 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)), 473 TII (nullptr), TRI(nullptr), 481 TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
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H A D | R600Packetizer.cpp | 62 const R600RegisterInfo &TRI; member in class:__anon26118::R600PacketizerList 67 return TRI.getHWRegChan(MI->getOperand(0).getReg()); 111 switch (TRI.getHWRegChan(Dst)) { 155 TRI(TII->getRegisterInfo()) {
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H A D | AMDGPUInstrInfo.cpp | 111 const TargetRegisterInfo *TRI) const { 120 const TargetRegisterInfo *TRI) const {
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H A D | R600EmitClauseMarkers.cpp | 184 const R600RegisterInfo &TRI = TII->getRegisterInfo(); local 189 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
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H A D | SILowerControlFlow.cpp | 70 const SIRegisterInfo *TRI; member in class:__anon26128::SILowerControlFlowPass 96 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } 407 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0); 428 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0); 444 TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.cpp | 668 const TargetRegisterInfo *TRI = TM->getRegisterInfo(); local 675 Instr->getRegClassConstraint(OpIdx, TII, TRI); 770 const TargetRegisterInfo *TRI = &getRegisterInfo(); local 774 if (Instr.modifiesRegister(AArch64::NZCV, TRI) || 775 Instr.readsRegister(AArch64::NZCV, TRI)) 892 MI->addRegisterDefined(AArch64::NZCV, TRI); 1176 const TargetRegisterInfo *TRI) const { 1194 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize(); 1258 const TargetRegisterInfo *TRI) { 1263 return MIB.addReg(TRI [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 58 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local 59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
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H A D | HexagonInstrInfo.h | 87 const TargetRegisterInfo *TRI) const override; 98 const TargetRegisterInfo *TRI) const override;
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/external/llvm/lib/Target/Mips/ |
H A D | Mips16FrameLowering.cpp | 107 const TargetRegisterInfo *TRI) const { 135 const TargetRegisterInfo *TRI) const {
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXPrologEpilogPass.cpp | 52 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); local 63 TRI.eliminateFrameIndex(MI, 0, i, nullptr);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 158 const TargetRegisterInfo *TRI) const override; 164 const TargetRegisterInfo *TRI) const override;
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H A D | PPCFrameLowering.cpp | 257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local 270 unsigned RegNo = TRI->getEncodingValue(I->first); 286 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 1188 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); local 1208 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1253 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1254 TRI->getEncodingValue(MinG8R)); 1362 const TargetRegisterInfo *TRI) const { 1417 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1419 CSI[i].getFrameIdx(), RC, TRI); [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 176 const TargetRegisterInfo *TRI) const override; 181 const TargetRegisterInfo *TRI) const override;
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