Searched refs:TRI (Results 151 - 175 of 233) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DLiveIntervalUnion.h95 // Print union, using TRI to translate register names
96 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
H A DMachineInstrBundle.h207 PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI);
H A DFastISel.h61 const TargetRegisterInfo &TRI; member in class:llvm::FastISel
H A DLiveIntervalAnalysis.h54 const TargetRegisterInfo* TRI; member in class:llvm::LiveIntervals
H A DMachineTraceMetrics.h70 const TargetRegisterInfo *TRI; member in class:llvm::MachineTraceMetrics
/external/llvm/lib/CodeGen/
H A DIfConversion.cpp163 const TargetRegisterInfo *TRI; member in class:__anon25750::IfConverter
274 TRI = MF.getTarget().getRegisterInfo();
1051 Redefs.init(TRI);
1057 DontKill.init(TRI);
1070 RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
1178 Redefs.init(TRI);
1332 Redefs.init(TRI);
1363 DontKill.init(TRI);
1392 RemoveKills(BBI1->BB->begin(), BBI1->BB->end(), DontKill, *TRI);
1434 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSel
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H A DMachineBasicBlock.cpp293 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local
298 OS << ' ' << PrintReg(*I, TRI);
826 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); local
832 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
1162 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1177 MIOperands(I).analyzePhysReg(Reg, TRI);
1198 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1215 MIOperands(I).analyzePhysReg(Reg, TRI);
H A DMachineFunction.cpp353 const TargetRegisterInfo *TRI = getTarget().getRegisterInfo(); local
359 OS << PrintReg(I->first, TRI);
361 OS << " in " << PrintReg(I->second, TRI);
603 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); local
604 BitVector BV(TRI->getNumRegs());
611 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
H A DMachineScheduler.cpp870 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
894 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
902 dbgs() << TRI->getRegPressureSetName(
926 DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
939 DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
940 if (!TRI->isVirtualRegister(Reg))
1117 if (!TRI->isVirtualRegister(Reg))
1235 const TargetRegisterInfo *TRI; member in class:__anon25770::LoadClusterMutation
1239 : TII(tii), TRI(tri) {}
1254 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
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H A DScheduleDAG.cpp40 TRI(TM.getRegisterInfo()),
352 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
372 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
H A DMachineSink.cpp48 const TargetRegisterInfo *TRI; member in class:__anon25775::MachineSinking
218 TRI = TM.getRegisterInfo();
H A DSplitKit.h218 const TargetRegisterInfo &TRI; member in class:llvm::SplitEditor
H A DTailDuplication.cpp64 const TargetRegisterInfo *TRI; member in class:__anon25829::TailDuplicatePass
139 TRI = MF.getTarget().getRegisterInfo();
146 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
801 BitVector RegsLiveAtExit(TRI->getNumRegs());
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp92 const TargetRegisterInfo &TRI,
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
152 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
1089 MachineFunction &MF, const TargetRegisterInfo *TRI,
1156 const TargetRegisterInfo *TRI) const {
1186 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1189 TRI);
1201 const TargetRegisterInfo *TRI) const {
1218 const TargetRegisterClass *RC = TRI
90 findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetRegisterInfo &TRI, bool Is64Bit) argument
149 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, int64_t NumBytes, bool Is64Bit, bool IsLP64, bool UseLEA, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) argument
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp183 const TargetRegisterInfo *TRI) const {
209 const TargetRegisterInfo *TRI) const {
H A DMSP430InstrInfo.cpp41 const TargetRegisterInfo *TRI) const {
69 const TargetRegisterInfo *TRI) const{
/external/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp618 const TargetRegisterInfo *TRI) const {
670 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
694 const TargetRegisterInfo *TRI) const {
739 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
740 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp411 const TargetRegisterInfo *TRI) const {
432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
433 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
447 const TargetRegisterInfo *TRI) const{
460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
461 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
H A DXCoreInstrInfo.cpp373 const TargetRegisterInfo *TRI) const
396 const TargetRegisterInfo *TRI) const
/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp69 const TargetRegisterInfo *TRI; member in struct:__anon25980::ARMLoadStoreOpt
721 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
1392 unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
1393 unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
1457 (TRI->regsOverlap(EvenReg, BaseReg))) {
1458 assert(!TRI->regsOverlap(OddReg, BaseReg));
1557 if (TRI->regsOverlap(Reg, I->MBBI->getOperand(0).getReg())) {
1731 TRI = TM.getRegisterInfo();
1768 const TargetRegisterInfo *TRI; member in struct:__anon25981::ARMPreAllocLoadStoreOpt
1811 IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSet<MachineInstr*, 4> &MemOps, SmallSet<unsigned, 4> &MemRegs, const TargetRegisterInfo *TRI) argument
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H A DARMFrameLowering.cpp965 const TargetRegisterInfo *TRI) {
1037 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1055 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1067 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1086 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1124 const TargetRegisterInfo *TRI) {
1155 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1171 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1182 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1196 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
961 emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
1120 emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
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/external/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
228 const TargetRegisterInfo *TRI, int64_t Offset) const {
549 const TargetRegisterInfo &TRI = getRegisterInfo(); local
566 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
588 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
226 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp118 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
120 if (TRI->isVirtualRegister(Reg)) {
695 const TargetRegisterInfo *TRI = &getRegisterInfo(); local
699 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
708 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
717 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
726 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
854 const TargetRegisterInfo *TRI) const {
949 const TargetRegisterInfo *TRI) const {
1424 const TargetRegisterInfo *TRI local
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/external/llvm/lib/Target/R600/
H A DR600MachineScheduler.cpp31 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
H A DSIISelLowering.cpp312 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); local
417 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
1267 const SIRegisterInfo &TRI = TII->getRegisterInfo(); local
1277 return TRI.getPhysRegClass(Reg);
1285 return TRI.getRegClass(OpClassID);
1299 return TRI.getRegClass(OpClassID);
1304 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1308 return TRI.getRegClass(
1318 const TargetRegisterInfo *TRI local
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