Searched refs:MRI (Results 226 - 247 of 247) sorted by path

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/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1633 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { argument
1638 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1639 E = MRI.def_instr_end(); I != E; ++I) {
1697 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
1698 return regIsPICBase(BaseReg, MRI);
1717 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
1718 return regIsPICBase(BaseReg, MRI);
2985 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
2987 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI
3012 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
3872 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const argument
5390 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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H A DX86InstrInfo.h418 const MachineRegisterInfo *MRI,
436 const MachineRegisterInfo *MRI) const override;
446 const MachineRegisterInfo *MRI,
H A DX86RegisterInfo.cpp427 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local
431 if (!MRI->canReserveReg(FramePtr))
437 return MRI->canReserveReg(BasePtr);
H A DX86VZeroUpper.cpp108 static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) { argument
109 for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(),
110 E = MRI.livein_end(); I != E; ++I)
254 MachineRegisterInfo &MRI = MF.getRegInfo(); local
264 if (!MRI.reg_nodbg_empty(*i)) {
285 if (checkFnHasLiveInYmm(MRI))
/external/llvm/lib/Target/XCore/InstPrinter/
H A DXCoreInstPrinter.h27 const MCRegisterInfo &MRI)
28 : MCInstPrinter(MAI, MII, MRI) {}
26 XCoreInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/llvm/lib/Target/XCore/MCTargetDesc/
H A DXCoreMCTargetDesc.cpp56 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, argument
88 const MCRegisterInfo &MRI,
90 return new XCoreInstPrinter(MAI, MII, MRI);
84 createXCoreMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp227 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); local
268 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
293 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
308 MRI->getDwarfRegNum(FramePtr, true));
319 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
329 MRI->getDwarfRegNum(SpillList[0].Reg, true),
332 MRI->getDwarfRegNum(SpillList[1].Reg, true),
/external/llvm/tools/llvm-mc/
H A DDisassembler.cpp165 std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple));
166 if (!MRI) {
171 std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, Triple));
178 MCContext Ctx(MAI.get(), MRI.get(), nullptr);
H A Dllvm-mc.cpp387 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
388 assert(MRI && "Unable to create target register info!");
390 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
405 MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
452 TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
461 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
462 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
472 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, *STI, Ctx);
473 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
/external/llvm/tools/llvm-objdump/
H A DMachODump.cpp223 std::unique_ptr<const MCRegisterInfo> MRI(
226 TheTarget->createMCAsmInfo(*MRI, TripleName));
229 MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr);
234 AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI, *STI));
H A Dllvm-objdump.cpp290 std::unique_ptr<const MCRegisterInfo> MRI(
292 if (!MRI) {
299 TheTarget->createMCAsmInfo(*MRI, TripleName));
319 MCContext Ctx(AsmInfo.get(), MRI.get(), MOFI.get());
347 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
389 mcmodule2yaml(YAMLOut, *Mod, *MII, *MRI);
/external/llvm/tools/llvm-rtdyld/
H A Dllvm-rtdyld.cpp327 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
328 assert(MRI && "Unable to create target register info!");
330 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName));
333 MCContext Ctx(MAI.get(), MRI.get(), nullptr);
342 TheTarget->createMCInstPrinter(0, *MAI, *MII, *MRI, *STI));
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_debug.cpp236 OwningPtr<const MCRegisterInfo> MRI(T->createMCRegInfo(Triple));
237 if (!MRI) {
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp317 MachineRegisterInfo &MRI = MF.getRegInfo(); local
319 if (!MRI.isLiveIn(Reg)) {
320 VirtualRegister = MRI.createVirtualRegister(RC);
321 MRI.addLiveIn(Reg, VirtualRegister);
323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
H A DAMDGPUInstrInfo.cpp241 MachineRegisterInfo &MRI = MF.getRegInfo(); local
249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
254 MRI.setRegClass(MO.getReg(), newRegClass);
H A DR600ISelLowering.cpp57 MachineRegisterInfo &MRI = MF->getRegInfo(); local
111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
120 unsigned NewAddr = MRI.createVirtualRegister(
122 unsigned ShiftValue = MRI.createVirtualRegister(
157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
260 MachineRegisterInfo &MRI = MF.getRegInfo(); local
263 if (!MRI
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H A DR600ISelLowering.h42 MachineRegisterInfo & MRI, unsigned dword_offset) const;
H A DSIAssignInterpRegs.cpp38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo(); local
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI
122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument
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H A DSIISelLowering.cpp69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo(); local
127 LowerSI_INTERP(MI, *BB, I, MRI);
130 LowerSI_INTERP_CONST(MI, *BB, I, MRI);
133 LowerSI_KIL(MI, *BB, I, MRI);
136 LowerSI_V_CNDLT(MI, *BB, I, MRI);
150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
183 MachineRegisterInfo &MRI) const
189 unsigned M0 = MRI
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H A DSIISelLowering.h33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/
H A DAMDGPUInstPrinter.h14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
13 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp68 const MCRegisterInfo &MRI,
70 return new AMDGPUInstPrinter(MAI, MII, MRI);
64 createAMDGPUMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument

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