Searched refs:MRI (Results 26 - 50 of 247) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
H A DNVPTXFrameLowering.cpp44 MachineRegisterInfo &MRI = MF.getRegInfo(); local
49 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass);
58 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass);
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp57 MachineRegisterInfo *MRI; member in struct:__anon25963::A15SDOptimizer
140 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
158 MachineInstr *MI = MRI->getVRegDef(SReg);
225 II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
257 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
258 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
277 MRI->getRegClass(MI->getOperand(1).getReg());
278 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
309 MachineInstr *Def = MRI
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H A DMLxExpansionPass.cpp53 MachineRegisterInfo *MRI; member in struct:__anon26004::MLxExpansion
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
102 DefMI = MRI->getVRegDef(Reg);
108 DefMI = MRI->getVRegDef(Reg);
120 !MRI->hasOneNonDBGUse(Reg))
124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
131 !MRI->hasOneNonDBGUse(Reg))
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
149 MachineInstr *DefMI = MRI->getVRegDef(Reg);
160 DefMI = MRI
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/external/llvm/lib/CodeGen/
H A DVirtRegMap.cpp56 MRI = &mf.getRegInfo();
84 unsigned Hint = MRI->getSimpleHint(VirtReg);
93 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
121 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
126 << MRI->getRegClass(Reg)->getName() << "\n";
130 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
134 << "] " << MRI->getRegClass(Reg)->getName() << "\n";
161 MachineRegisterInfo *MRI; member in class:__anon25833::VirtRegRewriter
210 MRI = &MF->getRegInfo();
234 MRI
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H A DMachineSink.cpp49 MachineRegisterInfo *MRI; // Machine register information member in class:__anon25775::MachineSinking
123 !MRI->hasOneNonDBGUse(SrcReg))
126 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
131 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
136 MRI->replaceRegWith(DstReg, SrcReg);
156 if (MRI->use_nodbg_empty(Reg))
175 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
188 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
219 MRI
399 AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) argument
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H A DDeadMachineInstructionElim.cpp34 const MachineRegisterInfo *MRI; member in class:__anon25737::DeadMachineInstructionElim
73 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
92 MRI = &MF.getRegInfo();
104 LivePhysRegs = MRI->getReservedRegs();
134 MRI->markUsesInDebugValueAsUndef(Reg);
H A DLLVMTargetMachine.cpp169 const MCRegisterInfo &MRI = *getRegisterInfo(); local
178 MII, MRI, STI);
183 MCE = getTarget().createMCCodeEmitter(MII, MRI, STI, *Context);
185 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
197 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, STI,
199 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
268 const MCRegisterInfo &MRI = *getRegisterInfo(); local
270 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), MRI,
272 MCAsmBackend *MAB = getTarget().createMCAsmBackend(MRI, getTargetTriple(),
H A DPeepholeOptimizer.cpp109 MachineRegisterInfo *MRI; member in class:__anon25783::PeepholeOptimizer
181 const MachineRegisterInfo *MRI; member in class:__anon25783::ValueTracker
211 /// \p MRI useful to perform some complex checks.
214 const MachineRegisterInfo *MRI = nullptr)
216 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI) {
273 if (MRI->hasOneNonDBGUse(SrcReg))
279 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
290 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
295 for (MachineInstr &UI : MRI
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H A DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
96 if (MRI.isConstantPhysReg(MO.getReg(), *OrigMI->getParent()->getParent()))
171 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
259 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
262 for (MCRegUnitIterator Units(Reg, MRI.getTargetRegisterInfo());
279 (MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) ||
324 if (LIS.hasInterval(Reg) && MRI
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H A DMachineCSE.cpp46 MachineRegisterInfo *MRI; member in class:__anon25762::MachineCSE
125 if (!MRI->hasOneNonDBGUse(Reg))
129 MachineInstr *DefMI = MRI->getVRegDef(Reg);
141 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
151 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
152 if (!MRI->constrainRegClass(SrcReg, RC))
157 MRI->clearKillFlags(SrcReg);
225 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
277 if (MRI->isAllocatable(PhysDefs[i]) || MRI
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H A DMachineSSAUpdater.cpp43 MRI = &MF.getRegInfo();
59 VRC = MRI->getRegClass(VR);
117 MachineRegisterInfo *MRI,
119 unsigned NewVR = MRI->createVirtualRegister(RC);
153 VRC, MRI, TII);
189 Loc, VRC, MRI, TII);
290 Updater->VRC, Updater->MRI,
301 Updater->VRC, Updater->MRI,
324 return InstrIsPHI(Updater->MRI->getVRegDef(Val));
114 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
H A DRegisterPressure.cpp85 PSetIterator PSetI = MRI->getPressureSets(RegUnits[i]);
99 decreaseSetPressure(CurrSetPressure, MRI->getPressureSets(RegUnits[I]));
190 MRI = &MF->getRegInfo();
205 LiveRegs.VirtRegs.setUniverse(MRI->getNumVirtRegs());
207 UntiedDefs.setUniverse(MRI->getNumVirtRegs());
297 increaseSetPressure(LiveThruPressure, MRI->getPressureSets(Reg));
314 const MachineRegisterInfo *MRI; member in class:RegisterOperands
324 TRI(tri), MRI(mri), IgnoreDead(ID) {}
349 else if (MRI->isAllocatable(Reg)) {
386 const MachineRegisterInfo *MRI) {
385 addPressureChange(unsigned RegUnit, bool IsDec, const MachineRegisterInfo *MRI) argument
411 collectPDiff(PressureDiff &PDiff, RegisterOperands &RegOpers, const MachineRegisterInfo *MRI) argument
882 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
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/external/llvm/lib/Target/R600/
H A DR600OptimizeVectorRegisters.cpp49 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { argument
50 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg),
51 E = MRI.def_instr_end(); It != E; ++It) {
54 if (MRI.isReserved(Reg)) {
66 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { argument
71 if (isImplicitlyDef(MRI, MO.getReg()))
86 MachineRegisterInfo *MRI; member in class:__anon26117::R600VectorRegMerger
190 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
217 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
218 E = MRI
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H A DSIInstrInfo.cpp193 MachineRegisterInfo &MRI = MF->getRegInfo(); local
203 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
218 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
371 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local
377 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))
736 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local
740 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
761 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local
772 unsigned Reg = MRI.createVirtualRegister(VRC);
779 MachineRegisterInfo &MRI,
778 buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument
804 buildExtractSubRegOrImm( MachineBasicBlock::iterator MII, MachineRegisterInfo &MRI, MachineOperand &Op, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const argument
826 split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist, MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineOperand &Op) const argument
857 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); local
1180 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local
1371 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
1423 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
1485 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
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/external/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.cpp65 const MCRegisterInfo &MRI,
68 return new MSP430InstPrinter(MAI, MII, MRI);
61 createMSP430MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/Sparc/InstPrinter/
H A DSparcInstPrinter.h29 const MCRegisterInfo &MRI,
31 : MCInstPrinter(MAI, MII, MRI), STI(sti) {}
27 SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &sti) argument
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h73 const MCRegisterInfo &MRI,
78 const MCRegisterInfo &MRI,
/external/llvm/lib/Target/R600/MCTargetDesc/
H A DSIMCCodeEmitter.cpp41 const MCRegisterInfo &MRI; member in class:__anon26111::SIMCCodeEmitter
52 : MCII(mcii), MRI(mri) { }
70 const MCRegisterInfo &MRI,
73 return new SIMCCodeEmitter(MCII, MRI, Ctx);
177 return MRI.getEncodingValue(MO.getReg());
69 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
H A DR600MCCodeEmitter.cpp36 const MCRegisterInfo &MRI; member in class:__anon26110::R600MCCodeEmitter
41 : MCII(mcii), MRI(mri) { }
84 const MCRegisterInfo &MRI,
86 return new R600MCCodeEmitter(MCII, MRI);
163 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
167 return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
176 return MRI.getEncodingValue(MO.getReg());
83 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp65 MachineRegisterInfo *MRI; member in struct:__anon26012::HexagonHardwareLoops
302 MRI = &MF.getRegInfo();
355 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
363 if (MRI->getVRegDef(IndReg) == Phi) {
382 MachineInstr *PredI = MRI->getVRegDef(PredR);
418 IVOp = MRI->getVRegDef(F->first);
469 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
501 MachineInstr *CondI = MRI->getVRegDef(PredReg);
593 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
596 OldInsts.push_back(MRI
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/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.h64 std::unique_ptr<const llvm::MCRegisterInfo> MRI; member in class:llvm::LLVMDisasmContext
99 MRI.reset(mRI);
117 const MCRegisterInfo *getRegisterInfo() const { return MRI.get(); }
/external/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AsmBackend.cpp301 const MCRegisterInfo &MRI; member in class:__anon25956::DarwinAArch64AsmBackend
311 DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI) argument
312 : AArch64AsmBackend(T), MRI(MRI) {}
374 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
386 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
387 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
408 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
415 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
546 const MCRegisterInfo &MRI,
545 createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
557 createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp64 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
67 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
70 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
73 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
76 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
79 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
82 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
85 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
88 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
91 } else if (MRI
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DR600ISelLowering.h42 MachineRegisterInfo & MRI, unsigned dword_offset) const;
/external/llvm/include/llvm/CodeGen/
H A DLiveRangeEdit.h62 MachineRegisterInfo &MRI; member in class:llvm::LiveRangeEdit
121 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
125 ScannedRemattable(false) { MRI.setDelegate(this); }
127 ~LiveRangeEdit() { MRI.resetDelegate(this); }

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